F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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4.1.2.2. VirtIO Registers

The following VirtIO capability structure registers references apply to each PF and VF. Addresses shown are register addresses.

Table 28.  PF/VF Capability Link List when VirtIO is enabled
Capability Start Byte Address Last Byte Address DW Count
Type0 0x00 0x3F 16
PM (PF only) 0x40 0x47 2
VirtIO Common Configuration 0x48 0x57 4
VirtIO Notifications 0x58 0x6B 5
Reserved 0x6C 0x6F 1
PCIe 0x70 0xA3 13
Reserved 0xA4 0xAF 3
MSIX 0xB0 0xBB 3
VirtIO ISR Status 0xBC 0xCB 4
VirtIO Device-Specific Configuration 0xCC 0xDB 4
VirtIO PCI Configuration Access 0xDC 0xEF 5
Reserved 0xF0 0xFF 4
Table 29.  VirtIO Capability Structures
Address Name Description
VirtIO Common Configuration Capability Structure
012 Common Configuration Capability Register Capability ID, next capability pointer, capability length
013 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
014 BAR Offset Register Indicates starting address of the structure within the BAR
015 Structure Length Register Indicates length of structure
VirtIO Notifications Capability Structure
016 Notifications Capability Register Capability ID, next capability pointer, capability length
017 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
018 BAR Offset Register Indicates starting address of the structure within the BAR
019 Structure Length Register Indicates length of structure
01A Notify Off Multiplier Multiplier for queue_notify_off
VirtIO ISR Status Capability Structure
02F ISR Status Capability Register Capability ID, next capability pointer, capability length
030 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
031 BAR Offset Register Indicates starting address of the structure within the BAR
032 Structure Length Register Indicates length of structure
VirtIO Device-Specific Capability Structure (Optional)
033 Device Specific Capability Register Capability ID, next capability pointer, capability length
034 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
035 BAR Offset Register Indicates starting address of the structure within the BAR
036 Structure Length Register Indicates length of structure
VirtIO PCI Configuration Access Structure
037 PCI Configuration Access Capability Register Capability ID, next capability pointer, capability length
038 BAR Indicator Register Lower 8 bits indicate which BAR holds the structure
039 BAR Offset Register Indicates starting address of the structure within the BAR
03A Structure Length Register Indicates length of structure
03B PCI Configuration Data Data for BAR access
Table 30.  VirtIO Common Configuration Capability Register (Address: 0x012)
Bit Location Description Access Type Default Value
31:24 Configuration Type RO 0x01
23:16 Capability Length RO 0x10
15:8 Next Capability Pointer RO 0x58
7:0 Capability ID RO 0x09
Note: The capability register identifies that this is a vendor-specific capability. It also identifies the structure type.
Table 31.  VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
Bit Location Description Access Type Default Value
31:24 Padding RO 0x00
23:16 Padding RO 0x00
15:8 Padding RO 0x00
7:0 BAR Indicator RO Programmable
Note: The Bar Indicator field holds the values 0x0 to 0x5 specifying a Base Address register (BAR) belonging to the function located beginning at 10h in PCI Configuration Space. The BAR is used to map the structure into the memory space. Any other value is reserved for future use.
Table 32.  VirtIO Common Configuration BAR Offset Register (Address: 0x014)
Bit Location Description Access Type Default Value
31:0 BAR Offset RO Programmable
Note: This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.
Table 33.  VirtIO Common Configuration Structure Length Register (Address: 0x015)
Bit Location Description Access Type Default Value
31:0 Structure Length RO Programmable
Note: The capability register identifies that this is a vendor-specific capability. It also identifies the structure type.
Table 34.  VirtIO Notifications Capability Register (Address: 0x016)
Bit Location Description Access Type Default Value
31:24 Configuration Type RO 0x02
23:16 Capability Length RO 0x14
15:8 Next Capability Pointer RO 0xBC
7:0 Capability ID RO 0x09
Note: The capability register identifies that this is a vendor-specific capability. It also identifies the structure type.
Table 35.  VirtIO Notifications BAR Indicator Register (Address: 0x017)
Bit Location Description Access Type Default Value
31:24 Padding RO 0x00
23:16 Padding RO 0x00
15:8 Padding RO 0x00
7:0 BAR Indicator RO Programmable
Note: The Bar Indicator field holds the values 0x0 to 0x5 specifying a Base Address register (BAR) belonging to the function located beginning at 10h in PCI Configuration Space. The BAR is used to map the structure into memory space. Any other value is reserved for future use.
Table 36.  VirtIO Notifications BAR Offset Register (Address: 0x018)
Bit Location Description Access Type Default Value
31:0 BAR Offset RO 31:0
Note: This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.
Table 37.  VirtIO Notifications Structure Length Register (Address: 0x019)
Bit Location Description Access Type Default Value
31:0 Structure Length RO 31:0
Note: The length register indicates the length of the structure. The length may include padding, fields unused by the driver, or future extensions.
Table 38.  VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
Bit Location Description Access Type Default Value
31:0 Multiplier for queue_notify_off RO 31:0
Note: The notify off multiplier register indicates the multiplier for queue_notify_off in the structure.
Table 39.  VirtIO ISR Status Capability Register (Address: 0x02F)
Bit Location Description Access Type Default Value
31:24 Configuration Type RO 0x03
23:16 Capability Length RO 0x10
15:8 Next Capability Pointer RO If Device-Specific Capability is present, then points to 0xCC, else points to 0xDC.
7:0 Capability ID RO 0x09
Note: The capability register identifies that this is a vendor-specific capability. It also identifies the structure type.
Table 40.  VirtIO ISR Status BAR Indicator Register (Address: 0x030)
Bit Location Description Access Type Default Value
31:24 Padding RO 0x00
23:16 Padding RO 0x00
15:8 Padding RO 0x00
7:0 BAR Indicator RO Programmable
Note: The Bar Indicator field holds the values 0x0 to 0x5 specifying a Base Address register (BAR) belonging to the function located beginning at 10h in PCI Configuration Space. The BAR is used to map the structure into memory space. Any other value is reserved for future use.
Table 41.  VirtIO ISR Status BAR Offset Register (Address: 0x031)
Bit Location Description Access Type Default Value
31:0 BAR Offset RO Programmable
Note: This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.
Table 42.  VirtIO ISR Status Structure Length Register (Address: 0x032)
Bit Location Description Access Type Default Value
31:0 Structure Length RO Programmable
Note: The length register indicates the length of the structure. The length may include padding, fields unused by the driver, or future extensions.
Table 43.  VirtIO Device Specific Capability Register (Address: 0x033)
Bit Location Description Access Type Default Value
31:24 Configuration Type RO 0x04
23:16 Capability Length RO 0x10
15:8 Next Capability Pointer RO 0xDC
7:0 Capability ID RO 0x09
Note: The capability register identifies that this is a vendor-specific capability. It also identifies the structure type.
Table 44.  VirtIO Device Specific BAR Indicator Register (Address: 0x034)
Bit Location Description Access Type Default Value
31:24 Padding RO 0x00
23:16 Padding RO 0x00
15:8 Padding RO 0x00
7:0 BAR Indicator RO Programmable
Note: The BAR Indicator field holds the values 0x0 to 0x5 specifying a Base Address register (BAR) belonging to the function located beginning at 10h in PCI Configuration Space. The BAR is used to map the structure into memory space. Any other value is reserved for future use.
Table 45.  VirtIO Device Specific BAR Offset Register (Address: 0x035)
Bit Location Description Access Type Default Value
31:0 BAR Offset RO Programmable
Note: This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.
Table 46.  VirtIO Device Specific Structure Length Register (Address: 0x036)
Bit Location Description Access Type Default Value
31:0 Structure Length RO Programmable
Note: The length register indicates the length of the structure. The length may include padding, fields unused by the driver, or future extensions.
Table 47.  VirtIO PCI Configuration Access Capability Register (Address: 0x037)
Bit Location Description Access Type Default Value
31:24 Configuration Type RO 0x05
23:16 Capability Length RO 0x14
15:8 Next Capability Pointer RO 0x00
7:0 Capability ID RO 0x09
Note: The capability register identifies that this is a vendor-specific capability. It also identifies the structure type.
Table 48.  VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
Bit Location Description Access Type Default Value
31:24 Padding RO 0x00
23:16 Padding RO 0x00
15:8 Padding RO 0x00
7:0 BAR Indicator RWS Undetermined
Note: The BAR Indicator field holds the values 0x0 to 0x5 specifying a Base Address register (BAR) belonging to the function located beginning at 10h in PCI Configuration Space. The BAR is used to map the structure into memory space. Any other value is reserved for future use.
Note: Register attribute RWS means RW with sticky behavior. It doesn’t get reset by FLR, Hot Reset nor Warm Reset.
Table 49.  VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
Bit Location Description Access Type Default Value
31:0 BAR Offset RWS Undetermined
Note: This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.
Note: Register attribute RWS means RW with sticky behavior. It doesn’t get reset by FLR, Hot Reset nor Warm Reset.
Table 50.  VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
Bit Location Description Access Type Default Value
31:0 Structure Length RWS Undetermined
Note: The length register indicates the length of the structure. The length may include padding, fields unused by the driver, or future extensions.
Note: Register attribute RWS means RW with sticky behavior. It doesn’t get reset by FLR, Hot Reset nor Warm Reset.
Table 51.  VirtIO PCI Configuration Access Data Register (Address: 0x03B)
Bit Location Description Access Type Default Value
31:0 PCI Configuration Data RWS Undetermined
Note: The PCI configuration data register indicates the data for BAR access.
Note: Register attribute RWS means RW with sticky behavior. It doesn’t get reset by FLR, Hot Reset nor Warm Reset.

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