F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.2. Data Link Layer

The Data Link Layer (DLL) is located between the Transaction Layer and the Physical Layer. It maintains packet integrity and communicates (by DLL packet transmission) at the PCIe Link.

The DLL implements the following functions:
  • Power management of DLLP reception and transmission
  • Transmit and receive ACK/NAK packets
  • Data integrity through the generation and checking of CRCs for TLPs andDLLPs
  • TLP retransmission in case of NAK DLLP reception or replay timeout, using the retry (replay) buffer
  • Management of the retry buffer
  • Link retraining requests in case of error through the Link Training and Status State Machine (LTSSM) of the Physical Layer
Figure 9. Data Link Layer
The DLL includes the following blocks:
  • Data Link Control and Management State Machine: This state machine connects to both the Physical Layer’s LTSSM state machine and the Transaction Layer. It initializes the link and flow control credits and reports status to the Transaction Layer.
  • Power Management: It handles the handshake to enter low power mode. Such a transition is based on register values in the Configuration Space and received Power Management (PM) DLLPs.
  • Data Link Layer Packet Generator and Checker: This block is associated with the DLLP’s 16-bit CRC and maintains the integrity of transmitted packets.
  • Transaction Layer Packet Generator: This block generates transmit packets, including a sequence number and a 32-bit Link CRC (LCRC). The packets are also sent to the retry buffer for internal storage. In retry mode, the TLP generator receives the packets from the retry buffer and generates the CRC for the transmit packet.
  • Retry Buffer: The retry buffer stores TLPs and re-transmits all unacknowledged packets in the case of NAK DLLP reception. In case of ACK DLLP reception, the retry buffer discards all acknowledged packets.
  • ACK/NAK Packets: The ACK/NAK block handles ACK/NAK DLLPs and generates the sequence number of transmitted packets.
  • Transaction Layer Packet Checker: This block checks the integrity of the received TLP and generates a request for transmission of an ACK/NAK DLLP.
  • TX Arbitration: This block arbitrates transactions, prioritizing in the following order:
    • Initialize FC Data Link Layer packet
    • ACK/NAK DLLP (high priority)
    • Update FC DLLP (high priority)
    • PM DLLP
    • Retry buffer TLP
    • TLP
    • Update FC DLLP (low priority)
    • ACK/NAK FC DLLP (low priority)