F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10. Revision History of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.04.04 22.1
2021.12.17 21.4
  • Release Information table updated for Intel® Quartus® Prime 21.4 release
  • Resource Utilization Information of the IP table added
  • TLP Bypass Mode section added to Advanced Features Chapter
  • F-Tile Debug Toolkit paramter information added to Top Level Settings table in Parameters Chapter
  • Screenshots updated in Core Parameters section of Parameters Chapter
  • Generating Tile Files information added to Testbench Chapter
  • Address Offsets and Bit Settings to enable and read LCRC and ECRC error count table updated
  • Example: To read the LCRC error count of x16 Port 0 using the registers steps updated
  • Debug Toolkit information added to Troubeshooting/Debugging Chapter
2021.10.22 21.3
  • RX Flow Control description updated
  • Buffer Limits Update example Figure updated in RX Flow Control
  • Credit Advertised by F-Tile PCIe Hard IP table added in RX Flow Control
  • Power Management section updated with new description
  • Variables Used in the Bus Indices Table updated
  • Timing Diagrams and tables added in Error Interface
  • 10-bit Tag Support Interface new section added
  • Power Management Interface Signals table updated in Power Management Interface
  • Hard IP Reconfiguration Interface Register Map for PHY Status table updated in AdditionalDebug Tools
  • Core Parameters section updated
  • Information to enable and read LCRC and ECRC error count added in Enable and Read LCRC and ECRC Error Count
  • New Appendix added Root Port Enumeration
2021.08.27 21.2 Initial Release