F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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5.17. FLR Interface Signals

Table 79.  FLR Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_flr_rcvd_pf_o[7:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

Active high signals. Once asserted, the signals remain high until the Application Layer sets the p#_flr_completed_pf_num_i[2:0] high for the associated function.

The Application Layer must perform actions necessary to clear any pending transactions associated with the function being reset. The Application Layer must assert p#_flr_completed_pf_num_i[2:0] to indicate it has completed the FLR actions and is ready to reenable the PF. These busses are differentiated by the prefixes p#.

p#_flr_rcvd_vf_o Output EP coreclkout_hip

Note: Not available for p2 and p3.

A one-cycle pulse indicates that an FLR was received from host targeting a VF. When port

bifurcation is used, there is one such signal for each Avalon-ST interface.

These signals are differentiated by the prefixes p#.

p#_flr_rcvd_pf_num_o[2:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

Parent PF number of the VF undergoing FLR. When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p#.

p#_flr_rcvd_vf_num_o[10:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

VF number offset of the VF undergoing FLR. When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p#.

p#_flr_completed_pf_i[7:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

One bit per PF. A one cycle pulse on any bit indicates that the application has completed the FLR sequence for the corresponding PF and is ready to be enabled.

When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p#.

p#_flr_completed_vf_i Input EP coreclkout_hip

Note: Not available for p2 and p3.

One-cycle pulse from the application re-enables a VF. When port bifurcation is used, there is one such signal for each Avalon-ST interface. These signals are differentiated by the prefixes p#.

The minimum separation between two consecutive pulses is 4 clocks.

p#_flr_completed_pf_num_i[2:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

Parent PF number of the VF to re-enable.When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes p#.

p#_flr_completed_vf_num_i[2:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

VF number offset of the VF to re-enable.When port bifurcation is used, there is one such bus for each Avalon-ST interface. These busses are differentiated by the prefixes. p#.

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