F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.1. Avalon Parameters

Table 85.   Avalon® Parameters
Parameter Value Default Value Description
Enable Power Management Interface and Hard IP Status Interface True/False False

When enabled, the Power Management Interface and Hard IP Status Interface are exported.

In addition, options are provided to to add the following signals for power management depending on the selected port mode of the IP:
  • p#_app_ready_entr_l23_i
  • p#_app_xfer_pending_i
  • p#_apps_pm_xmt_turnoff_i
Enable Legacy Interrupt True/False False

Enable the support for legacy interrupts.

Enable Completion Timeout Interface True/False False Enable the Completion Timeout Interface.
Enable Configuration Intercept Interface True/False False Enable the Configuration Intercept Interface.
Note: This parameter is only available in EP mode.
Enable PRS Event True/False False Enable the Page Request Service (PRS) Event Interface.
Note: This parameter is only available in EP mode.
Enable Error Interface True/False False

Enable the Error Interface.

Enable 10-bit tag support interface True/False False

When this parameter is enabled, the 10-bit tag requester enable signal is enabled as an output port p#_10bits_tag_req_en_o[7:0] (one bit per PF).

Enable Byte Parity Ports on Avalon® -ST Interface True/False False When this parameter is enabled, the byte parity ports appear on the block symbol. These byte parity ports include: rx_st_data_par_o, rx_st_hdr_par_o, rx_st_tlp_prfx_par_o, tx_st_data_par_o, tx_st_hdr_par_o, and tx_st_tlp_prfx_par_o ports.

Did you find the information on this page useful?

Characters remaining:

Feedback Message