126.96.36.199. Direct User Avalon-MM Interface (Byte Access)
|Bit||Name||Description||Access Type||Default Value|
|28:18||k_vf||Select the virtual function number||RW||0x000|
|17||k_vf_select||To access the virtual function registers, this bit should be set to one.||RW||0x0|
Valid only when d_vsec_select is zero.
If set, it allows the access to shadow registers in PCIe configuration space.
If cleared, it allows the access to standard PCIe configuration registers.
If set, it allows the acess to Intel VSEC registers
For Physical Function's configuration space registers access, your application needs to specify the offsets of the targeted Physical Function registers. For example, if the application wants to read the MSI Capability Register of Physical Function 0, it issues a read with address 0x0050 to target the MSI Capability Structure of Physical Function 0.
- Issue a user Avalon-MM Write request with address 0x1406A and data 0xE ( vf_num[28:18] = 3, vf _select = 1, vsec=0).
- Issue a user Avalon-MM Read request with address 0xB0 to access VF3 registers of Physical Function 0. In the case of Physical Function 1, the address is 0x10B0.
For Intel-defined VSEC access, your application needs to program the VSEC field (0x14068 bit) first. Then all accesses from the user Avalon-MM interface starting at offset 0xD00 is translated to VSEC configuration space registers.
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