F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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3.4.1. Legacy Interrupts

Legacy interrupts mimic the original PCI level-sensitive interrupts using virtual wire messages. The F-tile IP for PCIe signals legacy interrupts on the PCIe link using Message TLPs. The term INTx refers collectively to the four legacy interrupts: INTA#,INTB#, INTC# and INTD#. The F-tile IP for PCIe asserts app_int_i to cause an Assert_INTx Message TLP to be generated and sent upstream. A deassertion of app_int_i, a transition of this signal from high to low, causes a Deassert_INTx Message TLP to be generated and sent upstream. To use legacy interrupts, you must clear the Interrupt Disable bit, which is bit 10 of the Command Register in the configuration header. Then, you must turn off the MSI Enable bit.

Figure 26. Generating an Assert_INTx Message TLP Using the app_int_i Signal
Note: app_int_i[0] is asserted for at least eight clock cycles to cause an Assert_INTx Message TLP to be generated and sent upstream for physical function 0. For a multifunctions implementation, app_int_i[0] is for physical function 0, app_int_i[1] is for physical function 1 and so on. Deasserting a app_int_i signal by driving it from high to low causes a Deassert_INTx Message TLP to be generated and sent upstream.

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