F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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5.20. VirtIO PCI Configuration Access Interface Signals

Table 82.  VirtIO PCI Configuration Access Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_virtio_pcicfg_vfaccess_o Output EP coreclkout_hip

Indicates the driver access is to a VF.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_vfnum_o.

p#_virtio_pcicfg_vfnum_o[VFNUM_WIDTH-1:0] Output EP coreclkout_hip

Indicates the corresponding Virtual Function number associated with the current Physical Function that the driver’s write or read access is targeting.

Validated by virtio_pcicfg_vfaccess_o and by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

p#_virtio_pcicfg_pfnum_o[PFNUM_WIDTH-1:0] Output EP coreclkout_hip

Indicates the corresponding Physical Function number that the driver’s write or read access is targeting.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

p#_virtio_pcicfg_bar_o[7:0] Output EP coreclkout_hip

Indicates the BAR holding the PCI configuration access structure. The driver sets the BAR to access by writing to cap.bar.

Values 0x0 to 0x5 specify a BAR belonging to the function located beginning at 10h in the PCI Configuration Space.

The BAR can be either 32-bit or 64-bit. Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_length_o[31:0] Output EP coreclkout_hip

Indicates the length of the structure. The length may include padding, or fields unused by the driver, or future extensions.

The driver sets the size of the access by writing 1, 2 or 4 to cap.length.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_baroffset_o[31:0] Output EP coreclkout_hip

Indicates where the structure begins relative to the base address associated with the BAR. The driver sets the offset within the BAR by writing to cap.offset.

Validated by driver write access to pci_cfg_data, or driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_cfgdata_o[31:0] Output EP coreclkout_hip

Indicates the data for BAR access. The pci_cfg_data will provide a window of size cap.length into the given cap.bar at offset cap.offset. Validated by driver write access to pci_cfg_data. The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_cfgwr_o Output EP coreclkout_hip Indicates driver write access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.
p#_virtio_pcicfg_cfgrd_o Output EP coreclkout_hip

Indicates driver read access to pci_cfg_data.

The corresponding PF or VF is identified from the value of virtio_pcicfg_p/vfnum_o.

p#_virtio_pcicfg_appvfnum_i[VFNUM_WIDTH-1:0]

Input EP coreclkout_hip

This is a dummy signal created for backward compatibility with P-Tile PCIe Hard IP. It can be safely ignored in new design.

p#_virtio_pcicfg_apppfnum_i[PFNUM_WIDTH-1:0] Input EP coreclkout_hip

This is a dummy signal created for backward compatibility with P-Tile PCIe Hard IP. It can be safely ignored in new design.

p#_virtio_pcicfg_rdack_i Input EP coreclkout_hip

Indicates an application read access data ack to store the config data in pci_cfg_data. User is required to assert rdack on every read access to pci_cfg_data. The corresponding Virtual Function is

identified from the value of virtio_pcicfg_appvfnum_i.
p#_virtio_pcicfg_rdbe_i[3:0] Input EP coreclkout_hip

Indicates application enabled bytes within virtio_pcicfg_data_i.

Validated by virtio_pcicfg_rdack_i.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_appvfnum_i.

p#_virtio_pcicfg_data_i[31:0] Input EP coreclkout_hip

Indicates application data to be stored in PCI Configuration Access data registers.

Validated by virtio_pcicfg_rdack_i and virtio_pcicfg_rdbe_i.

The corresponding Virtual Function is identified from the value of virtio_pcicfg_appvfnum_i.

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