ID 683140
Date 4/04/2022
Public

## 7.2. Endpoint Testbench

The example design and testbench are dynamically generated based on the configuration that you choose for the F-Tile IP for PCIe. The testbench uses the parameters that you specify in the Parameter Editor in Intel® Quartus® Prime.

This testbench simulates up to a x16 PCI Express link using the serial PCI Express interface. The testbench design does allow more than one PCI Express link to be simulated at a time. The following figure presents a high level view of the design example.
Figure 66. Design Example for Endpoint Designs

The top-level of the testbench instantiates the following main modules:

• altpcietb_bfm_rp_gen4_x16.sv —This is the Root Port PCIe* BFM.
//Directory path
<project_dir>/pcie_avst_f_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_<ver>
• pcie_ed_dut.ip: This is the Endpoint design with the parameters that you specify.
//Directory path
<project_dir>/pcie_avst_f_0_example_design/ip/pcie_ed
• pcie_ed_pio0.ip: This module is a target and initiator of transactions for the PIO design example.
//Directory path
<project_dir>/intel_pcie_ftile_ast_0_example_design/ip/pcie_ed