F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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8.1.1.3.2. Enable and Read LCRC and ECRC Error Count

Table 113.  Address Offsets and Bit Settings to enable and read LCRC and ECRC error count
Offset Bit Position Register
Offset x16 (Port 0) Offset x8 (Port 1) Offset x4 (Ports 2, 3)
0x00119 0x00119 0x00119 [0] Enable CRC Check
0x0033C 0x00304 0x002B0 [1:0]

Event counter clear

Set to 2’b01 to clear error counter defined in registers 0x0033F and 0x0033E

Set to 2’b11 to clear all error counters

[4:2]

Event counter enable

Set to 3‘b111

0x0033D 0x00305 0x002B1 [7:0]

Event counter lane select

Set to x00

0x0033E 0x00306 0x002B2 [7:0]

Event number

For LCRC error count, set to 0x01

For ECRC error count, set to 0x02

0x0033F 0x00307 0x002B3 [7:0]

Group number

For LCRC error count, set to 0x02

For ECRC error count, set to 0x03

000x340 0x00308 0x002B4 [7:0] Error counter data bit [7:0]
0x00341 0x00309 0x002B5 [7:0] Error counter data bit [15:8]
0x00342 0x0030A 0x002B6 [7:0] Error counter data bit [23:16]
0x00343 0x0030B 0x002B7 [7:0] Error counter data bit [31:24]

Follow the steps below to access registers in above table using the Hard IP reconfiguration interface

  1. Enable the Hard IP reconfiguration interface (User Avalon-MM interface) using the IP Parameter Editor.
  2. Enable CRC check by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  3. Set the group number by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  4. Set the event number by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  5. Set the event counter lane select by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  6. Set event counter enable by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data on p#_hip_reconfig_writedata[7:0].
  7. Read the error count data by a read operation from the address hip_reconfig_address[20:0].

Example: To read the LCRC error count of x16 Port 0 using the registers

  1. Enable the Hard IP reconfiguration interface (User Avalon-MM interface) using the IP Parameter Editor.
  2. Perform read-modify-write to address 0x00119 to enable CRC check.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x00119
    • p0_hip_reconfig_writedata[7:0] = 8'h01
  3. Perform read-modify-write to address 0x00033F to set Group number.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x0033F
    • p0_hip_reconfig_writedata[7:0] = 8'h02
  4. Perform read-modify-write to address 0x00033E to set Event number.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x0033E
    • p0_hip_reconfig_writedata[7:0] = 8'h01
  5. Perform read-modify-write to address 0x00033D to set Event counter lane select.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x0033D
    • p0_hip_reconfig_writedata[7:0] = 8'h00
  6. Perform read-modify-write to address 0x00033C to set enable event counter.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x0033C
    • p0_hip_reconfig_writedata[7:0] = 8'h1C
  7. Read the error counter data by performing a read operation from registers 0x340, 0x341, 0x342, and 0x343.

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