F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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5.4.2. Avalon-ST TX Interface Signals

Table 63.  Avalon-ST TX Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_tx_st_data_i[w*128-1:0] Input EP/RP/BP coreclkout_hip

Application Layer data for transmission. The Application Layer must provide a properly formatted TLP on the TX interface. Valid when the corresponding tx_st_valid_i signal is asserted.

The mapping of message TLPs is the same as the mapping of Transaction Layer TLPs with 4-dword headers. The number of data cycles must be correct for the length and address fields in the header. Issuing a packet with an incorrect number of data cycles results in the TX interface hanging and becoming unable to accept further requests.

Note: There must be no Idle cycle between the tx_st_sop_i and tx_st_eop_i cycles unless there is backpressure with the deassertion of tx_st_ready_o.

p#_tx_st_sop_i[n-1:0] Input EP/RP/BP coreclkout_hip

Indicate the first cycle of a TLP when asserted in conjunction with the corresponding bit of tx_st_valid_i.

For the x16 configuration:
  • tx_st_sop_i[1]: When asserted, indicates the start of aTLP in tx_st_data_i[511:256].
  • tx_st_sop_i[0]: When asserted, indicates the start of a TLP in tx_st_data_i[255:0].

These signals are asserted for one clock cycle per each TLP. They also qualify the corresponding tx_st_hdr_i and tx_st_tlp_prfx_i signals.

p#_tx_st_eop_i[n-1:0] Input EP/RP/BP coreclkout_hip

Indicate the last cycle of a TLP when asserted in conjunction with the corresponding bit of tx_st_valid_i.

For the x16 configuration:
  • tx_st_eop_i[1]: When asserted, indicates the end of a TLP in tx_st_data_i[511:256].
  • tx_st_eop_i[0]: When asserted, indicates the end of a TLP in tx_st_data_i[255:0].

These signals are asserted for one clock cycle per each TLP.

p#_tx_st_valid_i[n-1:0] Input EP/RP/BP coreclkout_hip

Qualify the corresponding data segment of tx_st_data_i into the IP core on ready cycles.

To facilitate timing closure, it’s recommended that user register both the tx_st_ready_o and tx_st_valid_i signals.

Note: There must be no Idle cycle between the tx_st_sop_i and tx_st_eop_i cycles unless there is backpressure with the deassertion of tx_st_ready_o.

p#_tx_st_ready_o Output EP/RP/BP coreclkout_hip

Indicates that the PCIe Hard IP is ready to accept data for transmission. The readyLatency is three cycles.

If tx_st_ready_o is asserted by the Transaction Layer in the PCIe Hard IP on cycle <n>, then <n>+readyLatency is a ready cycle, during which the Application may assert tx_st_valid_i and transfer data.

If tx_st_ready_o is deasserted by the Transaction Layer on cycle <n>, then the Application must deassert tx_st_valid_i within the readyLatency number of cycles after cycle <n>.

tx_st_ready_o can be deasserted in the following conditions:
  • The LTSSM is not ready.
  • A Retry is in progress.
  • There are not enough credits available to send the request.
  • The F-Tile Avalon-ST IP is busy sending internally generated TLPs.
  • The internal F-Tile TX FIFO is full.
p#_tx_st_err_i[n-1:0] Input EP/RP/BP coreclkout_hip

When asserted, indicate an error in the transmitted TLP. These signals are asserted with tx_st_eop_i and nullify a packet.

tx_st_err_i[1]: When asserted, specifies an error in tx_st_data_i[511:256].

tx_st_err_i[0]: When asserted, specifies an error in tx_st_data_i[255:0].

p#_tx_st_hdr_i[n*128-1:0] Input EP/RP/BP coreclkout_hip
This is the header to be transmitted, which follows the TLP header format of the PCIe specifications except for the requester ID/completer ID fields (tx_st_hdr_i[95:80]):
  • tx_st_hdr_i[95:84]: tx_st_vf_num[11:0]
  • tx_st_hdr_i[83]: tx_st_vf_active
  • tx_st_hdr_i[82:80]: tx_st_func_num[2:0]

These signals are valid when the corresponding tx_st_sop_i signal is asserted.

The header uses a Big Endian implementation.

For TLP bypass, bit-127 is set to 1.

For EP/RP mode, bit-127 is set to 0.

p#_tx_st_tlp_prfx_i[n*32-1:0] Input EP/RP/BP coreclkout_hip

This is the TLP prefix to be transmitted, which follows the TLP prefix format of the PCIe specifications. PASID is included.

These signals are valid when the corresponding tx_st_sop_i signal is asserted.

The TLP prefix uses a Big Endian implementation (i.e. the Fmt field is in bits [31:29] and the Type field is in bits [28:24]).

If no prefix is present for a given TLP, that dword, including the Fmt field, is all zeros.

p#_tx_st_data_par_i[w*16-1:0] Input EP/RP/BP coreclkout_hip

Byte parity for tx_st_data_i. Bit[0] corresponds to tx_st_data_i[7:0], bit [1] corresponds to tx_st_data_i[15:8], and so on.

By default, the PCIe Hard IP generates the parity for the TX data.

However, when ECC is off, the parity can be passed in from the FPGA core by setting the k_pcie_parity_bypass register.

p#_tx_st_hdr_par_i[n*16-1:0] Input EP/RP/BP coreclkout_hip

Byte parity for tx_st_hdr_i. By default, the PCIe Hard IP generates the parity for the TX header.

However, when ECC is off, the parity can be passed in from the FPGA core by setting the k_pcie_parity_bypass register.

p#_tx_st_tlp_prfx_par_i[n*4-1:0] Input EP/RP/BP coreclkout_hip

Byte parity for tx_st_tlp_prfx_i. By default, the PCIe Hard IP generates the parity for the TX TLP prefix.

However, when ECC is off, the parity can be passed in from the FPGA core by setting the k_pcie_parity_bypass register.

p#_tx_par_err_o Output EP/RP/BP coreclkout_hip

Asserted for a single cycle to indicate a parity error during TX TLP transmission.

The IP core transmits TX TLP packets even when a parity error is detected.

Table 64.  TX Flow Control Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_tx_cdts_limit_tdm_idx_o[2:0] Output EP/RP/BP coreclkout_hip

Indicate the traffic type for the tx_cdts_limit_o[15:0] signals. This interface provides credit limit information for all enabled ports in a TDM manner.

The following encodings are defined:
  • 000: P header credit limit
  • 001: NP header credit limit
  • 010: CPL header credit limit
  • 011: reserved
  • 100: P data credit limit
  • 101: NP data credit limit
  • 110: CPL data credit limit
  • 111: reserved
p#_tx_cdts_limit_o[15:0] Output EP/RP/BP coreclkout_hip

Indicate the Flow Control (FC) credit units advertised by the remote Receiver.

These signals represent the total number of FC credits made available by the Receiver since Flow Control initialization.

Initially, these signals indicate the number of FC credits available in the remote Receiver. The value of these signals always increments and rolls over.

For example, if the remote Receiver advertises an initial Non-Posted Header (NPH) FC credit of 0xFFFF, after it receives a MRd request, the NPH FC credits value increments by 1 and rolls over to 0x0000. The tx_cdts_limit_tdm_idx_o[2:0]signals determine the traffic type.

When the traffic type is header credit, only the LSB 12 bits are valid.

Note that, in addition to the TLPs transmitted by the user application, internally generated TLPs also consume FC credits.

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