F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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Document Table of Contents

8.1.1.3.1. Using the Hard IP Reconfiguration Interface

Refer to the section Hard IP Reconfiguration Interface for details on this interface and the associated address map.

The following table lists the address offsets and bit settings for the PHY status registers. Use the Hard IP Reconfiguration Interface to access these read-only registers.

Table 112.  Hard IP Reconfiguration Interface Register Map for PHY Status
Offset x16 (Port 0) Offset x8 (Port 1) Offset x4 (Ports 2, 3) Bit Position Register
0x003EA 0x003B2 0x0035E [0] RX polarity
[1] RX detection
[2] RX Valid
[3] RX Electrical Idle
[4] TX Electrical Idle
0x003EC 0x003B4 0x00360 [7] Framing error
0x003ED 0x003B5 0x00361 [7] Lane reversal

Follow the steps below to access registers in above table using the Hard IP reconfiguration interface

  1. Enable the Hard IP reconfiguration interface (User Avalon® -MM interface) using the IP Parameter Editor.
  2. Set the lane number for which you want to read the status by performing a read-modify-write to the address p#_hip_reconfig_address[20:0] with write data of lane number on p#_hip_reconfig_writedata[7:0] using the Hard IP reconfiguration interface signals.
    • p#_hip_reconfig_write = 1’b1
    • p#_hip_reconfig_address[20:0] = <offset>
    • hip_reconfig_writedata[3:0] = <Lane number>, where Lane number = 4’h0 for lane 0, 4’h1 for lane 1, 4’h2 for lane 2, …
  3. Read the status of the register you want by performing a read operation from the address hip_reconfig_address[20:0] using the Hard IP reconfiguration interface signals.
    • p#_hip_reconfig_read = 1’b1
    • p#_hip_reconfig_address[20:0] = <offset>

      Offset = Refer to above table for the offset mapping.

    • p#_hip_reconfig_readdata[7:0] = Refer to table above for the bit position mapping.

Example: To read the RX detection status of x16 Port 0 Lane0 using the registers

  1. Enable the Hard IP reconfiguration interface using the IP Parameter Editor.
  2. Perform read-modify-write to address 0x0003E8 to set the lane number to 0 using the Hard IP reconfiguration interface signals.
    • p0_hip_reconfig_write = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x003E8
    • p0_hip_reconfig_writedata[3:0] = 4'h0
  3. Read the status of the RX detection register by performing a read operation from the address 0x0003EA[1] using the Hard IP reconfiguration interface signals.
    • p0_hip_reconfig_read = 1’b1
    • p0_hip_reconfig_address[20:0] = 0x003EA
    • p0_hip_reconfig_readdata[1] = 1'b1 (Far end receiver detected)

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