F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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5.12. Configuration Output Interface

The Transaction Layer configuration output (tl_cfg) bus provides a subset of the information stored in the Configuration Space. Use this information in conjunction with the app_err* signals to understand TLP transmission problems.

Table 74.  Configuration Output Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_tl_cfg_ctl_o[15:0] Output EP/RP/BP coreclkout_hip

Multiplexed data output from the register specified by tl_cfg_add_o[4:0].

The detailed information for each field in this bus is defined in Configuration Output Interface (COI).

p#_tl_cfg_add_o[4:0] Output EP/RP/BP coreclkout_hip

This address bus contains the index indicating which Configuration Space register information is being driven onto the tl_cfg_ctl_o[15:0] bits.

p#_tl_cfg_func_o[2:0] Output EP/RP/BP coreclkout_hip
Note: Not available for p2 and p3.
Specifies the function whose Configuration Space register values are being driven out on tl_cfg_ctl_o[15:0].
  • 3'b000: Physical Function 0 (PF0)
  • 3'b001: PF1and so on
p#_dl_timer_update_o Output EP/RP/BP coreclkout_hip

Active high pulse that asserts whenever the current link speed, link width, or max payload size changes.

When any of these parameters changes, the IP's internal Replay/ACK-NAK timers default back to their internally calculated PCIe tables.

To override these default values, reprogram the Port Logic register when these events occur.

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