5.5.1. Legacy Interrupt Interface Signals
|Signal Name||Direction||EP/RP/BP||Clock Domain||Description|
Note: Not available for p2 and p3.
When asserted, these signals indicate an assertion of an INTx message is requested. A transition from high to low indicates a deassertion of the INTx message is requested.
This bus is for EP only. Each bit is associated with a corresponding physical function. These signals must be asserted for at least 8 cycles.
These signals drive legacy interrupts to the Application Layer in Root Port mode.
The source of the interrupt will be logged in the Root Port Interrupt Status registers in the Port Configuration and Status registers.
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