F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

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5.9. Completion Timeout Interface

Table 71.  Completion Timeout Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_cpl_timeout_o Output EP/RP/BP coreclkout_hip

Indicates the event that the completion TLP for a request has not been received within the expected time window.

The IP core asserts this signal as long as the completion timeout FIFO in the Hard IP is not empty.

You can obtain more details about the completion timeout event by accessing Completion Timeout Register via User AVMM interface.

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