JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents PLL Reconfiguration Controller

The PLL reconfiguration controller (altera_pll_reconfig) facilitates dynamic real-time reconfiguration of the core PLL.

You can use this IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA. The PLL reconfiguration controller connects to the Nios II processor via the Avalon-MM interconnect. The Nios II processor sends dynamic reconfiguration instructions to the controller during a dynamic data rate reconfiguration operation. By default, the software does not contain any dynamic reconfiguration features but you can use the Qsys system to implement such feature in the software.