JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents Test Pattern Generator

The test pattern generator generates one of three patterns; parallel PRBS, alternate checkerboard, or ramp wave, and sends it along to the transport layer during test mode.

The test pattern generator has many customization options and you can modify the test pattern generator RTL to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. By default, the software does not contain any dynamic reconfiguration features but you can use the Qsys system to implement such feature in the software.

Note: The test pattern generator is implemented in the top level RTL file, not in the Qsys project.