JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents Design Example Parameters

The JESD204B IP parameter editor includes a Example Design tab for you to specify certain parameters before generating the design example.
Table 2.  Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings. When you select a design from the Preset library, this field shows the selected design.
Generate generic example design? Option to generate a generic design example. This parameter is available when the Select Design option displays None.
Example Design Files

The files to generate for different development phase.

Simulation—when selected, the necessary files for simulating the design example are generated.

Synthesis—when selected, the synthesis files are generated. Use these files to compile the design in the Quartus Prime software for hardware testing.

Generate HDL Format for Simulation The format of the RTL files for simulation—Verilog or VHDL.
Generate HDL Format for Synthesis The format of the RTL files for synthesis—Verilog or VHDL.
Target Development Kit Supported hardware for design implementation.