JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents

1.9. JESD204B IP Core Design Example User Guide Document Revision History

Date Version Changes
November 2017 2017.11.06
  • Added note stating CMU PLL is not applicable to Arria 10 devices in Supported JESD204B IP Core Parameter Configurations and IP Parameter Settings for Generic Design Example.
  • Added note to System Clocking for the Design Example table about additional jitter introduced to the ATX, fPLL, and transmit PLL output when using reference clock from a cascaded PLL output, global clock or core clock network.
May 2017 2017.05.08
  • Rebranded to Intel.
  • Added note to state the design example caters is applicable for Intel® Quartus® Prime Standard Edition only.
October 2016 2016.10.31
  • Updated supported configuration.
  • Updated supported parameter values for static reconfiguration.
  • Added note stating that the Qsys does not allow multiple system with same name in Nios II Subsystem in Qsys.
  • Added steps in Compiling and Simulating Design.
  • Updated document title.
May 2016 2016.05.02 Initial release.