JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents PLL

The design example requires four different clock domains—device clock, management clock, frame clock, and link clock.

Typically, the device clock is generated from an external converter or a clock device while the management clock (AVS clock) is generated from an on-board 100 MHz oscillator.

For instance, if the JESD204B IP core is configured at data rate of 6.144 Gbps, transceiver reference clock frequency of 153.6 MHz, and number of octets per frame (F) = 2, the example below indicates the PLL clock frequencies:

  • device clock = transceiver reference clock frequency = 153.6 MHz
  • link clock = 6144 / 40 = 153.6 MHz
  • frame clock = 153.6 x 32 / (8 x 2) = 307.2 MHz