JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Qsys System Component

The Qsys system instantiates both the JESD204B IP core data path and the Nios II subsystem control path.

Figure 26. Qsys System

The top level Qsys system, jesd204b_ed_qsys.qsys, instantiates the following modules:

  • JESD204B subsystem
  • Nios II subsystem
  • Core PLL
  • PLL reconfiguration controller
  • SPI master

The main data path flows through the JESD204B subsystem. In the example design, the JESD204B IP core is configured in duplex mode with both TX and RX data paths. On the TX data path, user data flows from the transport layer through the JESD204B IP core base module via a 32-bit per transceiver lane Avalon Streaming (Avalon-ST) interface and out as serial data to the external converters via the JESD204B IP core PHY module. On the RX data path, serial data flows from the external converters (or from the TX data path, in internal serial loopback mode) to the JESD204B IP core PHY module and out from the JESD204B IP core base module to the transport layer via a 32-bit per transceiver lane Avalon-ST interface.

The control path is centered on the Nios II processor in the Nios II subsystem and connects to various peripherals via the Avalon Memory-Mapped (Avalon-MM) interface. A secondary control path from the SPI master module links out to the SPI configuration interface of external converters via a 4-wire SPI interconnect. The configuration of the external converters is done by writing configuration data from the Nios II processor to the SPI master module. The SPI master module handles the serial transfer of data to the SPI interface on the converter end via the 4-wire SPI interconnect.

The core PLL generates the link clock and frame clock for the system. During a data rate dynamic reconfiguration process, the core PLL is dynamically reconfigurable at run time via the PLL reconfiguration controller.

To view the top level Qsys system in Qsys, follow these steps:

  1. Launch the Intel® Quartus® Prime software.
  2. On the File menu, click Open.
  3. Browse and select the jesd204b_ed_qsys.qsys file located in the project directory.
  4. Click Open to view the Qsys system.

You can access the address mapping of the submodules in the top level Qsys project by clicking on the Address Map tab in the Qsys window.

Figure 27. Address Map View in Qsys

The Qsys system supports multi-link scenarios (up to 16 links) using the existing address map. To add more links to the system, add more jesd204b_subsystem.qsys modules to the project, connect them to the jesd204b_subsystem Avalon-MM bridge, and adjust the address map accordingly. Bits 16-19 of the nios_subsystem-to-jesd204b_subsystem Avalon-MM bridge are reserved to support multi-links.