JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents Modifying the JESD204B IP Core Parameters Post-Generation

In the event that the design examples available does not suit your desired JESD204B IP parameter configuration, you can generate a generic example design and then manually modify the parameters to meet your specifications.
  1. Generate a generic design example with Nios II control unit.
  2. Open the top level Qsys system (jesd204b_ed_qsys.qsys) in Qsys.
  3. In the Qsys window, navigate to the File menu and click Open. Select jesd204b_subsystem.qsys and click Open.
  4. In the System Contents tab, double-click the jesd204b module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core. This is the duplicate JESD204B IP core that is generated in the design example folder, not the JESD204B IP core that is generated from the IP tab of the parameter editor, which is stored in a different folder.
  5. Modify the IP core parameters of the jesd204b module as per your system specifications. When you are done, navigate to the File menu and click Save.
  6. In the File menu, click Open. Select the top level Qsys project, jesd204b_ed_qsys.qsys and click Open.
  7. Verify that the jesd204b_subsystem.qsys project has been updated with the new IP parameters for the jesd204b module. Right-click the jesd204b_subsystem_0 module and select Drill into subsystem. The jesd204b_subsystem.qsys project opens in the Qsys window. In the System Contents tab, double-click on the jesd204b module and verify that the parameters in the parameters tab match the ones that you have updated earlier. When you are done verifying, click Move to the top of hierarchy to move back to the jesd204b_ed_qsys.qsys view.
  8. Click Generate HDL to generate the HDL files needed for Quartus compilation.
  9. After the HDL generation is completed, click Finish to save your Qsys settings and exit the Qsys window.
  10. You have to manually change the system parameters in the top level RTL file to match the parameters that you set in the Qsys project, if applicable. Open the top level RTL file ( in any text editor of your choice.
  11. Modify the system parameters at the top of the file to match the new JESD204B IP core settings in the Qsys project, if applicable. Refer to the Nios II Processor Design Example System Parameters for more details on the system parameters.
  12. Save the file and compile the design in Intel® Quartus® Prime software as per the instructions in the Compiling the Design Example for Synthesis.

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