JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017
Public

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1.6.5.2. Simulating the JESD204B IP Core Design Example

By default, the Intel® Quartus® Prime software generates simulator-specific scripts containing commands to compile, elaborate, and simulate Intel® FPGA IP models and simulation model library files. You can copy the commands into your simulation testbench script, or edit these files to add commands for compiling, elaborating, and simulating your design and testbench.

To simulate the design using the ModelSim- Intel® SE/AE simulator, follow these steps:

  1. Start the ModelSim- Intel® simulator.
  2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/mentor.
  3. On the File menu, click Load > Macro file. Select run_tb_top.tcl. This file compiles the design and runs the simulation automatically, providing a pass/fail indication on completion.

To simulate the design using the VCS MX simulator (in Linux), follow these steps:

  1. Start the VCS MX simulator.
  2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/synopsys/vcsmx.
  3. Run run_tb_top.sh. This file compiles the design and runs the simulation automatically, providing a pass/fail indication on completion.

To simulate the design using the Aldec Riviera-PRO simulator, follow these steps:

  1. Start the Aldec Riviera-PRO simulator.
  2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/aldec.
  3. On the Tools menu, click Execute Macro. Select run_tb_top.tcl. This file compiles the design and runs the simulation automatically, providing a pass/fail indication on completion.
Note: VHDL is not supported in Aldec Riviera (for Arria 10 devices only) simulator.