JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents

1.1.4. Compiling and Testing the Design

The JESD204B IP Core parameter editor allows you to compile and run the design example on a target development kit.

Follow these steps to compile and test the design in hardware:

  1. Launch the Intel® Quartus® Prime software and compile the design (Processing> Start Compilation).

    The timing constraints for the design example and the design components are automatically loaded during compilation.

  2. Connect the development board to the host computer.
  3. Configure the FPGA on the development board using the generated .sof file (Tools> Programmer).

    The Intel® Quartus® Prime version 15.1 only supports programming file generation for Arria 10 engineering devices. For more information on support for Arria 10 production devices, contact Intel.

For details on how to implement the JESD204B design example on the Arria 10 GX FPGA Development Kit, refer to Implementing the Design on the Development Kit.