JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017
Public

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1.7.9.2. Changing the Data Rate or Reference Clock Frequency

When changing the data rate or reference clock frequency, be aware of the relationships between the serial data rate, link clock, and frame clock as described in the Core PLL section and change the PLL output clock settings accordingly to meet the clock frequency requirements.
Also be aware of the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factor parameters for cases when F=1 or F=2. These parameters further divide down the frame clock frequency requirement so the resulting clock frequency is within bounds of the timing closure for the FPGA core fabric.

To change the serial data rate or reference clock frequency:

  1. Open the jesd204b_subsystem.qsys project in the Qsys window.
  2. Double-click the jesd204b module to bring up the parameters editor for the JESD204B IP core.
  3. Change the Data rate and PLL/CDR Reference Clock Frequency values to meet your system requirements.
  4. Double-click the xcvr_atx_pll_a10_0 module to bring up the parameters editor for the ATX PLL module. This is the module that generates the serial clock for the TX transceiver PHY.
  5. Under the PLL subtab, locate the Output Frequency group and change the PLL output frequency and PLL integer reference clock frequency values to meet your system requirements. Note that the PLL output frequency is half of the PLL output data rate as the clocking of the TX data is in DDR mode. Ensure that the data rate and PLL reference clock values match the parameters that were entered into the jesd204b module.
  6. Navigate back to the top level jesd204b_ed_qsys.qsys hierarchy.
  7. Double-click the core_pll module to bring up the parameters editor for the core PLL module.
  8. Under the PLL subtab, change the Reference Clock Frequency value in the General group to meet your system requirements. Ensure that the reference clock frequency value matches the ones set for the jesd204b and xcvr_atx_pll_a10_0 modules. Also change the outclk0 group settings (which correspond to the link clock) and outclk1 group settings (which correspond to the frame clock) where necessary. Ensure that the link_clk and frame_clk values satisfy the frequency requirements as described in the Core PLL section.
  9. Click Generate HDL to generate the design files needed for Intel® Quartus® Prime compilation.
  10. After the HDL generation is completed, click Finish to save your Qsys settings and exit the Qsys window.
  11. If the frame clock settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or F2_FRAMECLK_DIV values are 1, change the relevant system parameters in the top level design file, jesd204b_ed.sv.
  12. Save the file and compile the design.