JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

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Document Table of Contents Procedure

To compile and simulate the design:
  1. Change the working directory to <example_design_directory>/ed_sim/
  2. Type one of the following to generate the simulation files:
    • For verilog: quartus_sh -t gen_ed_sim_verilog.tcl
    • For vhdl: quartus_sh -t gen_ed_sim_vhdl.tcl
  3. Change the working directory to <example_design_directory>/ed_sim/testbench/<Simulator>.
  4. Run the simulation script for the simulator of your choice. Refer to the table below.
    Simulator Command
    Modelsim do run_tb_top.tcl
    VCS/VSCMX sh
    Aldec do run_tb_top.tcl
    NCSim sh
    A successful simulation ends with the following message, "Simulation stopped due to successful completion! Simulation passed."