JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Supported System Configuration

The transport layer supports static configurations where before compilation, you can modify the configurations using the IP core's parameter editor in the Intel® Quartus® Prime software. To change to another configuration, you have to recompile the design. The following list describes the supported configurations for the transport layer:

  • Data rate (maximum) = 12.5 Gbps (F1_FRAMECLK_DIV = 4 and F2_FRAMECLK_DIV = 2)
  • L = 1–8
  • F = 1, 2, 4, 8
  • N = 12, 13, 14, 15, 16
  • N' = 16
  • CS = 0–3
  • CF = 0
  • HD = 0 (for F=2, 4, 8), 1 (for F=1)

Dynamic Downscaling Of System Parameters (L, N, and F)

The Dynamic Downscaling of System Parameters (DDSP) feature enables you to dynamically downscale specific JESD204B system parameters through the CSR, without having to recompile the FPGA.

The transport layer supports dynamic downscaling of parameters L, F, and N only. The supported M and S parameters are determined by the L, F, and N' parameters. Some parameters (for example, CS and N') do not have this capability in the transport layer. If you needs to change any of these parameters, you must recompile the system.

You are advised to connect the power down channels to higher indexes and connect used channel at lower lanes. Otherwise, you have to reroute the physical-used channels to lower lanes externally when connecting the IP core to the transport layer. For example, when L = 4 and csr_l = 8'd1 (which means two lanes out of four lanes are active), with lane 1 and lane 3 being powered down, connection from the MAC to the transport layer for lane 0 remains. However, lane 1 is powered down while lane 2 is not powered down. Thus, lane 2 output from the MAC should be rerouted to lane 1 data input of the transport layer. The data port for those power-down channels will be tied off within the transport layer.

The 16-bit N' data for F = 1 is formed through the data from 2 lanes. Thus, F = 1 is not supported for odd number of lanes, for example, when LMF = 128. In this case, you can only reconfigure from F = 8 to F = 4 and F = 2 but not F = 1.

Relationship Between Frame Clock and Link Clock

The frame clock and link clock are synchronous.

The ratio of link_clk period to frame_clk period is given by this formula:

32 x L / (M x S x N')

Table 15.   txframe_clk and rxframe_clk Frequency for Different F Parameter Settings For a given f txlink (txlink_clk frequency) and f rxlink (rxlink_clk frequency), the f txframe (txframe_clk frequency) and f rxframe (rxframe_clk frequency) are derived from the formula listed in this table.
F Parameter f txframe (txframe_clk frequency) f rxframe (rxframe_clk frequency)
1 ftxlink x (4 / F1_FRAMECLK_DIV ) frxlink x (4 / F1_FRAMECLK_DIV )
2 ftxlink x (2 / F2_FRAMECLK_DIV ) frxlink x (2 / F2_FRAMECLK_DIV )
4 ftxlink frxlink
8 ftxlink / 2 frxlink / 2