JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017
Public

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1.2. Supported Configurations

The design examples only support a limited set of JESD204B IP core parameter configurations.
The IP Catalog parameter editor allows you to generate a design example only if the parameter configurations matches those in the tables below.
Table 3.  Supported JESD204B IP Core Parameter Configurations (L, M, F Values)
JESD204B IP Parameters Applicable Devices
L M F
1 1 2 V series and Intel® Arria® 10
1 1 4 V series and Intel® Arria® 10
1 1 8 Intel® Arria® 10
1 2 4 V series and Intel® Arria® 10
1 2 8 Intel® Arria® 10
1 4 8 V series and Intel® Arria® 10
2 1 1 V series and Intel® Arria® 10
2 1 2 V series and Intel® Arria® 10
2 1 4 V series and Intel® Arria® 10
2 1 8 Intel® Arria® 10
2 2 2 V series and Intel® Arria® 10
2 2 4 V series and Intel® Arria® 10
2 2 8 Intel® Arria® 10
2 4 4 V series and Intel® Arria® 10
2 4 8 Intel® Arria® 10
2 8 8 Intel® Arria® 10
4 1 1 Intel® Arria® 10
4 1 2 Intel® Arria® 10
4 2 1 V series and Intel® Arria® 10
4 2 2 V series and Intel® Arria® 10
4 2 4 Intel® Arria® 10
4 2 8 Intel® Arria® 10
4 4 2 V series and Intel® Arria® 10
4 4 4 V series and Intel® Arria® 10
4 4 8 Intel® Arria® 10
4 8 4 V series and Intel® Arria® 10
4 8 8 Intel® Arria® 10
4 16 8 Intel® Arria® 10
6 1 1 Intel® Arria® 10
6 3 1 Intel® Arria® 10
8 1 1 V series and Intel® Arria® 10
8 1 2 Intel® Arria® 10
8 2 1 V series and Intel® Arria® 10
8 2 2 Intel® Arria® 10
8 2 4 Intel® Arria® 10
8 4 1 V series and Intel® Arria® 10
8 4 2 V series and Intel® Arria® 10
8 4 4 Intel® Arria® 10
8 4 8 Intel® Arria® 10
8 8 2 Intel® Arria® 10
8 8 4 Intel® Arria® 10
8 8 8 Intel® Arria® 10
8 16 4 Intel® Arria® 10
8 16 8 Intel® Arria® 10
8 32 8 Intel® Arria® 10
Table 4.  Supported JESD204B IP Core Parameter Configurations
JESD204B IP Parameters Value
Wrapper Options Both Base and Phy
Data Path Duplex
JESD204B Subclass 1
Data Rate
  • 6144 (Arria V, Stratix V, and Arria 10)
  • 5000 (Cyclone V)
PCS Option Enabled Hard PCS
PLL Type CMU2
Bonding Mode
  • Bonded (For Enable Transceiver Dynamic Reconfiguration option set to No)
  • Non-bonded (For Enable Transceiver Dynamic Reconfiguration option set to Yes)
Enable Transceiver Dynamic Reconfiguration
  • No (Bonding Mode must be set to Bonded)
  • Yes (Bonding Mode must be set to Non-bonded)
  • For Arria 10:
    • No (only the RTL state machine control design example is available for generation)
    • Yes (only Nios control design example is available for generation)
PLL/CDR Reference Clock Frequency
  • 153.6 (Arria V, Stratix V, and Arria 10; all supported L parameter values except L=8)
  • 307.2 (Arria V, Stratix V, and Arria 10; L=8)
  • 125 (Cyclone V; all supported L parameter values except L=8)
  • 250 (Cyclone V; L=8)
Enable Bit Reversal And Byte Reversal No
N
  • 16 (V series)
  • 12, 13, 14, 15, 16 ( Intel® Arria® 10)
N’ 16
CS
  • 0 (V series)
  • 0-3 ( Intel® Arria® 10)
CF 0
High Density User Data Format (HD)
  • 0 (V series)
  • 0 for F = 2, 4, 8 ( Intel® Arria® 10)
  • 1 for F = 1 ( Intel® Arria® 10)
Enable scramble (SCR) Yes
Enable Error Code Correction (ECC_EN) Yes
Table 5.  Valid Options Available for Design Example Generation
Device Supported JESD204B IP Core Configurations Example Design Type Generate Generic Example Design? Example Design Files HDL Format Target Development Kit

Stratix V, Arria V, Cyclone V

No None No
No None Generic RTL Simulation Verilog, VHDL
No None Generic RTL Synthesis Verilog 3
Yes RTL Simulation Verilog, VHDL
Yes RTL Synthesis Verilog 3
Arria 10 No None No
No None Generic RTL Simulation Verilog, VHDL
No None Generic RTL Synthesis Verilog 3
No None Generic Nios Synthesis 4 Verilog 3
  • None
  • Arria 10 5
Yes RTL Simulation Verilog, VHDL
Yes RTL Synthesis Verilog 3
Yes Nios Synthesis 4 Verilog 3
  • None
  • Arria 10 5
2 Not applicable to Arria 10 devices.
3 For synthesis flow, only the Verilog HDL format is available.
4 For Nios II control unit example design option, only synthesis filesets are available and only Verilog HDL format is supported.
5 For Nios II control unit example design option, you can choose not to target your design to any development kit or choose to target the Arria 10 GX FPGA Development Kit.

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