Visible to Intel only — GUID: bhc1411117119306
Ixiasoft
Visible to Intel only — GUID: bhc1411117119306
Ixiasoft
1.6.4.2. MIF ROM
You need to generate two MIF files for each reconfigurable IP core as shown in Figure 23 or Figure 24, and merge them into a single MIF file for each IP core. The following section shows the MIF file format.
Core PLL
The MIF format is fixed by the PLL. You need to generate two PLLs with maximum and downscale setting to get these two MIF files. Then, merge the files into one (core_pll.mif). Only the PLL with maximum configuration is used in final compilation.
Maximum Configuration MIF WIDTH=32; DEPTH=92; ADDRESS_RADIX=UNS; DATA_RADIX=BIN; CONTENT BEGIN 0 : 00000000000000000000000000111110; -- START OF MIF 1 : 00000000000000000000000000000100; 2 : 00000000000000000000000100000001; 3 : 00000000000000000000000000000011; . . . 42 : 00000000000000000000000000000010; 43 : 00000000000000000000000000001000; 44 : 00000000000000000000000001000000; 45 : 00000000000000000000000000111111; -- END OF MIF
Downscale Configuration MIF 46 : 00000000000000000000000000111110; -- START OF MIF 47 : 00000000000000000000000000000100; 48 : 00000000000000000000000100000001; 49 : 00000000000000000000000000000011; . . . 88 : 00000000000000000000000000000010; 89 : 00000000000000000000000000001000; 90 : 00000000000000000000000001000000; 91 : 00000000000000000000000000111111; -- END OF MIF END;
PHY (Stratix V and Arria V)
The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum and downscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL and two for channel MIF). Then, merge the files into one (phy.mif). Only the JESD204B IP cores with maximum configuration is used in final compilation.
Maximum TX PLL Configuration MIF WIDTH=16; DEPTH=186; ADDRESS_RADIX=UNS; DATA_RADIX=BIN; CONTENT BEGIN 0 : 0000000000100001; -- Start of MIF opcode (TX_PLL, 6144Mbps) 1 : 0000000000100010; . . . 10 : 0011000000000000; 11 : 0000000000011111; -- End of MIF opcode
Maximum Channel Configuration MIF 12 : 0000000000100001; -- Start of MIF opcode (Channel, 6144Mbps) 13 : 0000000000000010; . . . [88..91] : 0000000000000000; 92 : 0000000000011111; -- End of MIF opcode
Downscale TX PLL Configuration MIF 93 : 0000000000100001; -- Start of MIF opcode (TX_PLL, 3072Mbps) 94 : 0000000000100010; . . . 103 : 0011000000000000; 104 : 0000000000011111; -- End of MIF opcode
Downscale Channel Configuration MIF 105 : 0000000000100001; -- Start of MIF opcode (Channel, 3072Mbps) 106 : 0000000000000010; . . . [181..184] : 0000000000000000; 185 : 0000000000011111; -- End of MIF opcode END;
PHY (Arria 10)
The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum and downscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL and two for channel MIF). Then, merge the files into two (xcvr_atx_pll_combined.mif and xcvr_cdr_combined.mif). Only the JESD204B IP cores with maximum configuration is used in final compilation.
xcvr_atx_pll_combined.mif Maximum Configuration MIF CONTENT BEGIN 00 : 102FF71; -- Start of MIF 01 : 103BF01; 02 : 1047F04; 03 : 1054700; . . . 10 : 11AFF00; 11 : 11CE020; 12 : 11DE020; 13 : 3FFFFFF; -- End of MIF
Downscale Channel Configuration MIF 14 : 102FF71; -- Start of MIF 15 : 103BF01; 16 : 1047F04; 17 : 1054700; . . . 24 : 11AFF00; 25 : 11CE020; 26 : 11DE020; 27 : 3FFFFFF; -- End of MIF END;
xcvr_cdr_combined.mif Maximum Configuration MIF CONTENT BEGIN 00 : 006DF02; -- Start of MIF 01 : 007FF09; 02 : 008FF04; 03 : 00AFF01; . . . 76 : 173FF31; 77 : 1741F0C; 78 : 1753F13; 79 : 3FFFFFF; -- End of MIF
Downscale Channel Configuration MIF 7A : 006DF02; -- Start of MIF 7B : 007FF09; 7C : 008FF04; 7D : 00AFF01; . . . F0 : 173FF31; F1 : 1741F0C; F2 : 1753F13; F3 : 3FFFFFF; -- End of MIF END;
JESD
The current JESD MIF contains only the LMF information. You need to manually code the MIF content in the following format.
Maximum Configuration MIF WIDTH=16; DEPTH=16; ADDRESS_RADIX=UNS; DATA_RADIX=BIN; CONTENT BEGIN 0 : 0000000000000001; -- L (maximum config) 1 : 0000000000000001; -- M 2 : 0000000000000001; -- F . . . 3 : 1111111111111111; -- End of MIF [4..7] : 0000000000000000;
Downscale Configuration MIF 8 : 0000000000000000; -- L (downscale config) 9 : 0000000000000000; -- M 10 : 0000000000000001; -- F . . . 11 : 1111111111111111; -- End of MIF [12..15] : 0000000000000000; END;
ADC/DAC/CLK
The content for ADC/DAC/CLK MIF is vendor-specific. The general format for the MIF is as shown below, with each section terminated by all 1's.
Maximum Configuration MIF WIDTH=32; DEPTH=128; ADDRESS_RADIX=UNS; DATA_RADIX=BIN; CONTENT BEGIN 0 : 10000100000000000001000001111100; -- (Maximum Config) 1 : 10000100000000000001010000000101; 2 : 10000100000000000001011000000101; 3 : 10000100000000000001110000000010; . . . 28 : 10000001000000001111111100000001; 29 : 10000001000000000101111100010100; 30 : 11111111111111111111111111111111; -- End of MIF [31..63] : 00000000000000000000000000000000;
Downscale Configuration MIF 64 : 10000100000000000001000001111100; -- (downscale config) 65 : 10000100000000000001010000000101; 66 : 10000100000000000001011000000101; 67 : 10000100000000000001110000000010; . . . 92 : 10000001000000001111111100000001; 93 : 10000001000000000101111100010100; 94 : 11111111111111111111111111111111; -- End of MIF 95..127] : 00000000000000000000000000000000; END;