1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
The JESD204B IP core is part of the MegaCore IP Library, which is distributed with the Quartus® II software and downloadable from the Altera website.
This reference design demonstrates the JESD204B IP core operating as part of a system that includes:
- Altera JESD204B transport layer (assembler and deassembler)
- test pattern generator and checker
- core PLL
- SPI master
- reset sequencer
- various dynamic reconfiguration controllers
- Nios® II processor as the control unit
The key feature of this reference design is the software-based control flow that utilizes the Nios II processor control unit.
The reference design utilizes the Arria 10 FPGA Development Kit to interoperate with the Analog Devices (ADI) AD9680 ADC daughter card connected to the development board.
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