AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.1. Reference Design Overview

Figure below shows a system level block diagram of the JESD204B reference design with the Nios II processor control unit. This design is implemented on the Arria 10 FPGA development board interoperating with the ADI AD9680 ADC converter card.

Figure 1. Block Diagram of the JESD204B Reference Design with Nios II Processor


Reference design blocks:

  • QSYS components:
    • JESD204B subsystem
    • Nios II subsystem
    • SPI master
    • Core PLL and core PLL reconfiguration controller
  • HDL components:
    • Altera transport layer (assembler and deassembler)
    • Test pattern generator and checker
  • Nios II subsystem generates SYSREF for the JESD204B IP core and the AD9680 module (for Subclass 1 mode).
  • The device_clk (153.6Mhz) that is sent to the FPGA from the AD9516 external clock module is the reference clock for the on-chip core PLL, ATX PLL (which supplies the serial clock to the TX transceiver) and RX transceiver PLL.
  • Core PLL module generates the link clock (link_clk) and frame clock (frame_clk).
  • Oscillator on-board the Arria-10 FPGA development board supplies a 100 MHz management clock (mgmt_clk) to clock the control plane.

AD9516 external clock module

  • Supplies a 614.4 MHz clock to the ADCs on the AD9680 module via an SMA connector.
  • Supplies a 153.6 MHz reference clock to the FPGA via an SMA connector on the AD9680 module. The reference clock is passed through from the AD9680 module to the FPGA via the FMC connector.
  • You can replace this module with any external clock module that supplies a 614.4 MHz and 153.6 MHz reference clock.

AD9680 module

  • Configured to transmit on 4 high-speed transceiver lanes (L=4) to the FPGA.
  • Each lane is configured to 6.144 Gbps data rate
  • Derives power from the FMC connector on the Arria 10 FPGA development board.
  • Passes the FPGA reference clock (device_clk) to the FPGA via the FMC connector.
Table 1.  System ClockingThis table summarizes the system clocking of the reference design.

Clocks

Description

Modules Clocked

device_clk

Reference clock to the FPGA

Core PLL, ATX PLL, RX transceiver PLL.

link_clk

Link layer clock

JESD204B IP core link layer, transport layer link interface.

frame_clk

Frame layer clock

Transport layer, test pattern generator and checker, downstream modules.

mgmt_clk

Control plane clock

Nios II subsystem and any modules connected to Nios II via Avalon-MM bus interconnect.

Did you find the information on this page useful?

Characters remaining:

Feedback Message