AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.4.1.1.2. Reset Sequencer

The reset sequencer generates the following system resets to reset various modules in the system:

  • Core PLL reset—resets the core PLL
  • Transceiver reset—resets the JESD204B IP core PHY module
  • TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core configuration status registers
  • TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer
  • TX/RX frame reset—resets the TX/RX transport layer and downstream modules

The reset sequencer has hard and soft reset options. The hard reset port connects to the PB0 push button on the Arria 10 FPGA development board. The soft reset option is executed by issuing the reset command via the terminal console in the Nios II SBT (Software Build Tools) for Eclipse tool. When you assert a hard reset, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.

Figure 4. Reset Sequence


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