AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.4.1.1. JESD204B Subsystem

The JESD204B subsystem Qsys project, jesd204b_subsystem.qsys, instantiates the following modules:

  • JESD204B IP core configured in duplex, non-bonded mode (with TX and RX datapaths)
  • Reset sequencer
  • Transceiver PHY reset controller
  • ATX PLL
  • Avalon-MM bridge
Table 2.  JESD204B IP Core Parameter Configuration

Parameter

Value

Description

Subclass

1

Subclass mode

L

4

Number of lanes per converter device

M

2

Number of converters per device

F

1

Number of octets per frame

S

1

Number of transmitted samples per converter per frame

N

14

Number of conversion bits per converter

N’

16

Number of transmitted bits per sample

K

32

Number of frames per multiframe

CS

0

Number of control bits per conversion sample

CF

0

Number of control words per frame clock period per link

HD

0

High Density user data format

SCR

Off

Enable scramble

FRAMECLK_DIV

4

The divider ratio of frame clock (used in transport layer assembler and deassembler modules)