AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.4.1.1. JESD204B Subsystem

The JESD204B subsystem Qsys project, jesd204b_subsystem.qsys, instantiates the following modules:

  • JESD204B IP core configured in duplex, non-bonded mode (with TX and RX datapaths)
  • Reset sequencer
  • Transceiver PHY reset controller
  • ATX PLL
  • Avalon-MM bridge
Table 2.  JESD204B IP Core Parameter Configuration

Parameter

Value

Description

Subclass

1

Subclass mode

L

4

Number of lanes per converter device

M

2

Number of converters per device

F

1

Number of octets per frame

S

1

Number of transmitted samples per converter per frame

N

14

Number of conversion bits per converter

N’

16

Number of transmitted bits per sample

K

32

Number of frames per multiframe

CS

0

Number of control bits per conversion sample

CF

0

Number of control words per frame clock period per link

HD

0

High Density user data format

SCR

Off

Enable scramble

FRAMECLK_DIV

4

The divider ratio of frame clock (used in transport layer assembler and deassembler modules)


Section Content
Configuring the JESD204B IP core parameters in QSYS
Reset Sequencer
Transceiver PHY Reset Controller and ATX PLL
JESD204B Subsystem Address Map

Level Two Title