AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.4.1.1.4. JESD204B Subsystem Address Map

You can access the address mapping of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the QSYS window. The memory allocation address map is described in the table below.

Table 3.  JESD204B Subsystem Address Map

Avalon-MM Peripheral

Address Map

JESD204B IP core transceiver reconfiguration interface

0x0000 – 0x3FFF

ATX PLL (up to 4 modules per link)

0x8000 – 0x8FFF (Module 0)

0x9000 – 0x9FFF (Module 1)

0xA000 – 0xAFFF (Module 2)

0xB000 – 0xBFFF (Module 3)

JESD204B IP core CSR – TX

0xC000 – 0xC3FF

JESD204B IP core CSR – RX

0xD000 – 0xD3FF

Reset sequencer

0xE000 – 0xE0FF

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