AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.4.1.1.4. JESD204B Subsystem Address Map

You can access the address mapping of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the QSYS window. The memory allocation address map is described in the table below.

Table 3.  JESD204B Subsystem Address Map

Avalon-MM Peripheral

Address Map

JESD204B IP core transceiver reconfiguration interface

0x0000 – 0x3FFF

ATX PLL (up to 4 modules per link)

0x8000 – 0x8FFF (Module 0)

0x9000 – 0x9FFF (Module 1)

0xA000 – 0xAFFF (Module 2)

0xB000 – 0xBFFF (Module 3)

JESD204B IP core CSR – TX

0xC000 – 0xC3FF

JESD204B IP core CSR – RX

0xD000 – 0xD3FF

Reset sequencer

0xE000 – 0xE0FF

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