AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.9. User Commands

The table below describes the commands that you can issue at the terminal console.

Table 10.  User Commands

Type

Command

Description

Help

h

Display menu of available commands.

Reset

r [link select #] [p | x | c | l | f | h | r]

Selective/global soft system reset. The [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command will take effect on all links identically. The [p | x | c | l | f ] options indicate the specific submodule that the reset command will take effect on:

[p] – Core PLL

[x] – TX/RX Transceivers (JESD204B IP core PHY)

[c] – TX/RX JESD204B IP core CSR

[l] – TX/RX link reset

[f] – TX/RX frame reset

If none of the options above are indicated, all submodules are reset. You can indicate multiple options simultaneously to perform simultaneous submodule resets.

The [h | r] options indicate if the reset is asserted and held or released from a hold:

[h] – Assert and hold reset

[r] – Release reset

If none of the options above are indicated, the resets are pulsed (asserted and released automatically).

When the [r] option is indicated, the reset is released immediately without checking for any qualifying conditions (for example, the PLL locked or transceiver ready signals). You are responsible to qualify the signals before holding or releasing the resets.

Reset

r [link select #] [p | x | c | l | f | h | r]

(continued)

Depending on the DATAPATH setting in the main.h file, the command takes effect on either the TX only datapath (if DATAPATH is set to TX only), the RX only datapath (if DATAPATH is set to RX only) or both TX and RX datapaths (if DATAPATH is set to duplex).

Command examples:

  • > r : This is a full auto-mode global reset that performs a series of initialization steps after global reset. The sequence of steps are:
    1. Global system reset on all links according to the hardware reset sequence (refer to Figure 1 for timing diagram of hardware reset sequence).
    2. Initialize link (set loopback and source/destination mode to default mode).
    3. Trigger SYSREF pulse (for Subclass 1 configuration).
    4. Wait 10 seconds.
    5. Report link status.
  • > r 2 h : Assert all submodule resets for link 2 and hold resets indefinitely.
  • > r r : Release all submodules resets for all links immediately and concurrently (no pre-set hardware sequence)
    Attention: Not recommended as no checking process for qualifying signals.
  • > r x l f h : Assert and hold transceiver, link, and frame resets for all links.
  • > r x r : Release (deassert) transceiver resets for all links (but keep other submodule resets on hold if previously held)
  • > r 2 l f : Pulse (assert and release) link and frame resets for link 2 (but keep other submodule resets on hold if previously held)

Load SPI

ls [slave select #] <offset> <value>

Loads 8-bit value <value> (in C-style “0x” hexadecimal notation) into the register of external converter module connected to the SPI interface at offset <offset> (in C-style “0x” hexadecimal notation) indicated by [slave select #]. The maximum bit width of <offset> is 16 bits.

Get SPI

gs [slave select #] <offset>

Gets the 8-bit value (in C-style “0x” hexadecimal notation) at the register of external converter module connected to SPI interface at offset <offset> (in C-style “0x” hexadecimal notation) indicated by [slave select #]. The maximum bit width of <offset> is 16 bits.

Config SPI

cs

Configure external converter modules via SPI interface.

Initialize

i [link select #] [n]

Initialize link indicated by [link select #]. The [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command takes effect on all links identically. By default, the link is initialized to test mode (see ‘Test’ command). The optional [n] option initializes the link to user mode (see ‘Test’ command).

Note: When setting to user mode, ensure that the user input data valid signal (avst_usr_din_valid) is properly connected in the top level HDL file (jesd204b_ed.sv). Failing to do so will result in continuous error interrupts and may cause the system to hang.

The full sequence of steps executed by this command:

  1. Set test or user mode (set loopback and source/destination mode) as per options indicated.
  2. Trigger SYSREF pulse (for Subclass 1 configuration).
  3. Wait 10 seconds.
  4. Report link status.

Status

s [link select #] [t | r]

Reports TX and/or RX link status of link indicated by [link select #]. Reads back tx_status0 and/or rx_status0 status registers from the JESD204B CSR identified by [link select #] and reports link status based on the values in those registers. For example, the command can report that the indicated link is not in sync or not in User Data Mode. In addition, the command reports the status of the pattern checker error signal. The [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command takes effect on all links identically. The optional [t | r] options indicates the datapath to be reported:

[t] – Report TX path status only

[r] – Report RX path status only

[no option] – Report default path status according to DATAPATH setting

Depending on the DATAPATH setting in the main.h file, the command will take effect on either the TX only datapath (if DATAPATH is set to TX only), the RX only datapath (if DATAPATH is set to RX only) or both TX and RX datapaths (if DATAPATH is set to duplex).

Loopback

lb [link select #] [n]

Puts the JESD204B IP core PHY indicated by [link select #] into transceiver serial loopback mode. This command is only applicable for links where the JESD204B IP core is configured in duplex mode (TX and RX datapaths present). The [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command takes effect on all links identically. The optional [n] option sets the JESD204B IP core PHY indicated by [link select #] into non-serial loopback mode.

Source/ Destination

sd [link select #] [s | d] [u | a | r | p]

Selects the source and destination datapath for the Avalon-ST interface of the link indicated by [link select #]. The [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command takes effect on all links identically. The optional [s | d] option indicates whether the source (TX) or destination (RX) datapath is being selected:

[s] – Source datapath (TX)

[d] – Destination datapath (RX)

[no option] – Default datapath according to DATAPATH setting

Depending on the DATAPATH setting in the main.h file, the command will take effect on either the TX only datapath (if DATAPATH is set to TX only), the RX only datapath (if DATAPATH is set to RX only) or both TX and RX datapaths (if DATAPATH is set to duplex).

The optional [u | a | r | p] option indicates the type of datapath to set to:

Note: When setting to user mode, ensure that the user input data valid signal (avst_usr_din_valid) is properly connected in the top level HDL file (jesd204b_ed.sv). Failing to do so will result in continuous error interrupts and may cause the system to hang.

[u] – User datapath (no test pattern generator and checker)

[a] – Test pattern generator and checker set to alternate pattern

[r] – Test pattern generator and checker set to ramp pattern

[p] – Test pattern generator and checker set to PRBS pattern

[no option] – Default to test pattern generator and checker set to PRBS pattern

The test pattern generator and checker module has other configurable parameters that you can set. In particular, the pattern generator and checker derives its M and S values from the JESD204B IP core CSR. Also, there are other parameters such as POLYNOMIAL_LENGTH and FEEDBACK_TAP that are set during compile time. Refer to Chapter 5 of the JESD204B IP Core User Guide for more details.

Test

t [link select #] [n]

Sets the link indicated by [link select #] to test mode. The [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command takes effect on all links identically. The test mode is defined by:

  • Source and destination datapath set to default (test pattern generator and checker set to PRBS pattern)
  • Transceiver set to serial loopback mode

The optional [n] option negates the test mode (set to user mode). User mode is defined as:

  • Source and destination datapath set to user datapath
  • Transceiver set to non-serial loopback mode
Note: When setting to user mode, ensure that the user input data valid signal (avst_usr_din_valid) is properly connected in the top level HDL file (jesd204b_ed.sv). Failing to do so will result in continuous error interrupts and may cause the system to hang.

Reinitialization

ri [link select #] [t | r]

Trigger a link reinitialization on links indicated by [link select #]. The optional [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command takes effect on all links identically. The optional [t | r] option indicates the type of reinitialization operation:

[t] – TX link reinitialization; TX link transmits K28.5 packets continuously until link is out of CGS (Code Group Synchronization) phase

[r] – RX link reinitialization; SYNC_N signal is driven low until link is out of CGS (Code Group Synchronization)
Note: Forcing RX link reinitialization will trigger a TX SYNCN error interrupt to the Nios II processor. The interrupt is automatically cleared by the software.

[no option] – For DATAPATH setting set to TX only or duplex, default to TX link reinitialization. For DATAPATH setting set to RX only, default to RX link reinitialization

For more details on the reinitialization operation, refer to the JESD204B IP Core User Guide.

Sysref

sy

Pulse SYSREF signal one time (“one-shot”)

Reconfiguration

rc [link select #]

[l <value>]

[m <value>]

[f <value>]

[s <value>]

[n <value>]

[np <value>]

[cs <value>]

[k <value>]

[hd <value>]

[scr <value>]

[sub <value>]

[dr <value>]

Dynamically reconfigure link indicated by [link select #] according to parameter-value pair option indicated. The optional [link select #] option selects the link that the command will take effect on. If no [link select #] option is indicated, the command takes effect on all links identically. The parameters that are dynamically configurable are as follows:

[l] – Lanes per converter device

[m] – Converters per device

[f] – Octets per frame

Note: The Altera test pattern generator and checker do not support dynamic reconfiguration of F.

[s] – Samples per converter per frame

[n] – Converter resolution

[np] – Transmitted bits per sample

[cs] – Control bits

[k] – Frames per multi-frame

[hd] – High density user data format

[scr] – Enable scrambler

[sub] – Subclass select

[dr] – Serial data rate

The valid value ranges that can be entered for each parameter are governed by rules enforced by software. Refer to the Dynamic Reconfiguration section for more details.

Command examples:

  • > rc l 2 m 2 f 2 : Reconfigure the JESD204B IP core to L=2, M=2, F=2.
  • > rc np 16 hd 1 : Reconfigure the JESD204B IP core to N’=16, HD=1.
  • > rc dr 2 : Reconfigure the link serial data rate to the initially configured data rate divide by 2.

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