AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.4.1.2. Nios II Subsystem

The Nios II subsystem Qsys project, nios_subsystem.qsys, instantiates the following peripherals:

  • Nios II processor
  • On-chip memory—provides both instruction and data memory space
  • Timer—provides a general timer function for software
  • JTAG UART—serves as the main communications portal between the user and the Nios II processor via the terminal console in NIOS II SBT for Eclipse tool
  • Avalon-MM bridges
  • PIO—provides general input/output (I/O) access from the Nios II processor to the HDL components in the FPGA via two sets of 32-bit registers:
    • io_status (status registers input from the HDL components to NIOS-II)
    • io_control (control registers output from NIOS-II to the HDL components)

The tables below describe the signal connectivity for the io_status and io_control registers.

Table 4.   Signal Connectivity for io_status Registers
Bit Signal
0 Core PLL locked
1 TX transceiver ready (Link 0)
2 RX transceiver ready (Link 0)
3 Test pattern checker data error (Link 0)
4–31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signals for subsequent links, if present.
Table 5.   Signal Connectivity for io_control Registers
Bit Signal
0 RX serial loopback enable for lane 0 (Link 0)
1 RX serial loopback enable for lane 1 (Link 0)
2 RX serial loopback enable for lane 2 (Link 0)
3 RX serial loopback enable for lane 3 (Link 0)
4–30 RX serial loopback enable for subsequent links, if present.
31 Sysref

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