AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.4.1.2. Nios II Subsystem

The Nios II subsystem Qsys project, nios_subsystem.qsys, instantiates the following peripherals:

  • Nios II processor
  • On-chip memory—provides both instruction and data memory space
  • Timer—provides a general timer function for software
  • JTAG UART—serves as the main communications portal between the user and the Nios II processor via the terminal console in NIOS II SBT for Eclipse tool
  • Avalon-MM bridges
  • PIO—provides general input/output (I/O) access from the Nios II processor to the HDL components in the FPGA via two sets of 32-bit registers:
    • io_status (status registers input from the HDL components to NIOS-II)
    • io_control (control registers output from NIOS-II to the HDL components)

The tables below describe the signal connectivity for the io_status and io_control registers.

Table 4.   Signal Connectivity for io_status Registers
Bit Signal
0 Core PLL locked
1 TX transceiver ready (Link 0)
2 RX transceiver ready (Link 0)
3 Test pattern checker data error (Link 0)
4–31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signals for subsequent links, if present.
Table 5.   Signal Connectivity for io_control Registers
Bit Signal
0 RX serial loopback enable for lane 0 (Link 0)
1 RX serial loopback enable for lane 1 (Link 0)
2 RX serial loopback enable for lane 2 (Link 0)
3 RX serial loopback enable for lane 3 (Link 0)
4–30 RX serial loopback enable for subsequent links, if present.
31 Sysref

Section Content
Nios II Subsystem Address Map

Level Two Title