AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL

The transceiver PHY reset controller takes the transceiver PHY reset output from the reset sequencer and generates the proper analog and digital reset sequencing for the transceiver PHY module. The ATX PLL supplies a low-jitter serial clock to the transceiver PHY module.

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