AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.7. Top Level HDL Parameters

The top level HDL file (jesd204b_ed.sv) located in the <project directory>/jesd204b_nios_ref_design/jesd204b_ed/ directory includes project parameters that define the configuration of the reference design as a whole. The parameters are described in the table below.

Table 9.   Top Level Parameters
Parameter Description
LINK Number of JESD204B links. Set to match the configuration in QSYS.
L Number of JESD204B lanes per converter device. Set to match the configuration in QSYS.
M Number of JESD204B converters per device. Set to match the configuration in QSYS.
F Number of JESD204B octets per frame. Set to match the configuration in QSYS.
N Number of JESD204B conversion bits per converter device. Set to match the configuration in QSYS.
N_PRIME Number of JESD204B transmitted bits per sample. Set to match the configuration in QSYS.
S Number of JESD204B transmitted samples per converter device per frame. Set to match the configuration in QSYS.
CS Number of JESD204B control bits per conversion sample. Set to match the configuration in QSYS.
F1_FRAMECLK_DIV Divider ratio for frame_clk when F=1. Refer to the JESD204B IP Core User Guide for more details.
F2_FRAMECLK_DIV Divider ratio for frame_clk when F=2. Refer to the JESD204B IP Core User Guide for more details.
POLYNOMIAL_LENGTH Defines the polynomial length for the PRBS pattern generator and checker. Refer to the JESD204B IP Core User Guide for more details.
FEEDBACK_TAP Defines the feedback tap for the PRBS pattern generator and checker. Refer to the JESD204B IP Core User Guide for more details.