AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules
1.4.1. Qsys System
1.4.1. Qsys System
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.12. AN 729 Document Revision History

Table 16.  Document Revision History
Date Version Changes
May 2015 2015.05.04 Updated the software requirement to Quartus II software version 15.0.
February 2015 2015.02.13 Initial release.
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