AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.4. System Modules

The reference design consists of the following key modules and sub-modules:

  • QSYS system
    • JESD204B subsystem
    • Nios II subsystem
    • Core PLL and PLL reconfiguration controller
    • SPI master
  • Transport layer
    • Assembler (TX data path)
    • Deassembler (RX data path)
  • Test pattern generator and checker

The transport layer (assembler and deassembler) and test pattern generator and checker modules are instantiated in the top level RTL (jesd204b_ed.sv).

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