AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

ID 683844
Date 5/04/2015
Public
Document Table of Contents

1.5. Reference Design Files

The reference design comes with a ZIP file that includes a Quartus II archive file (.qar) that contains:

  • Quartus II project files
  • source files
  • Qsys projects
  • ancillary files
  • system libraries

The ZIP file also contains the software C code that you can use to compile and download into the Nios II processor control unit. When restoring the archive file in the Quartus II software, create a destination folder and name it jesd204b_ed to store all the reference design files.

Table 6.  Reference Design FilesThis table lists the important folders and files that you may need to edit to customize the design.

File Type

File/Folder

Description

Quartus project files

jesd204b_ed.qpf

Quartus project file.

jesd204b_ed.qsf

Quartus settings file.

Verilog HDL design files

jesd204b_ed.sv

Top level HDL.

jesd204b_ed.sdc

Synopsys Design Constraints (SDC) file containing all timing/placement constraints.

transport_layer

Transport layer folder containing assembler and de-assembler HDL.

pattern

Pattern folder containing the test pattern generator and checker HDL. Contains HDL for loopback version and AD9680 test pattern generator and checker (files with _AD9680 suffix).

QSYS Projects

jesd204b_ed_qsys.qsys

Top level QSYS system project.

jesd204b_subsystem.qsys

JESD204B subsystem (refer to “JESD204B Subsystem” section)

nios_subsystem.qsys

Nios II subsystem (refer to “Nios II Subsystem” section)

Software files

software

Folder containing all software-related files (detailed description in Table 7.

Table 7.  Software File Directory

File Type

File

Description

Header files

altera_jesd204_qsys_regs.h

Offsets, masks, and bit position definitions for peripherals in QSYS system that do not have standard access libraries. This includes the following peripherals:

  • JESD204B TX and RX CSR
  • Reset sequencer
  • PIO control
  • PIO status
  • Core PLL reconfiguration

altera_xcvr_atx_pll_a10_

reconfig_parameters.h

RAM arrays that contain the dynamic reconfiguration address offsets and data values for the ATX PLL reconfiguration registers.

altera_xcvr_native_a10_

reconfig_parameters.h

RAM arrays that contain the dynamic reconfiguration address offsets and data values for the transceiver native PHY IP core reconfiguration registers.

main.h

General user parameter definitions.

functions.h

Contains function prototype definitions of sub-functions in main.c.

rules.h

Contains function prototype definitions of rule functions in rules.c.

macros.h

Contains function prototype definitions of macro functions in macros.c.

Source files

main.c

Main C program. Also contain sub functions.

rules.c

Rule checking functions used by the dynamic reconfiguration functions.

macros.c

JESD204B QSYS system device access macros.

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