F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents

4.4.5. Virtual Lane Order and Offset Values

As bit interleaving and lane distribution of virtual lanes and FEC lanes may be implemented differently in PCS and FEC of other devices, it is not possible to know the ordering implementation of data transmitted by link partner. Therefore the PTP implementation uses logical lane arrangement without interleaving. The tables below show examples of the virtual lane arrangement in 100GE (25GE-4 and 50GE-2) Ethernet rates.

Table 17.  Virtual Lane Distribution in Physical Lanes of 100GE (25GE-4) Ethernet Rate
Physical Lane T + 0 T + 1 T + 2 T + 3 T + 4
Lane 0 VL0 VL4 VL8 VL12 VL16
Lane 1 VL1 VL5 VL9 VL13 VL17
Lane 2 VL2 VL6 VL10 VL14 VL18
Lane 3 VL3 VL7 VL11 VL15 VL!9
Table 18.  Virtual Lane Distribution in Physical Lanes of 100GE (50GE-2) Ethernet Rate
Physical Lane T + 0 T + 1 T + 2 T + 3 T + 4 T + 5 T + 6 T + 7 T + 8 T + 9
Lane 0 VL0 VL2 VL4 VL6 VL8 VL10 VL12 VL14 VL16 VL18
Lane 1 VL1 VL3 VL5 VL7 VL9 VL11 VL13 VL15 VL17 VL19