F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

6. Resets

Ethernet reset ports control for the F-Tile Ethernet Intel® FPGA Hard IP consists of four main reset ports and five soft datapath and statistics register resets.
Figure 30. Conceptual Overview of General IP Core Reset Logic
The general reset signals reset the following functions:
  • i_reconfig_reset: Resets the entire reconfiguration clock domain, including the soft CSR registers and Avalon® memory-mapped interface.
  • i_tx_rst_n: Resets the TX datapath, TX transceivers, and TX EMIB adapters.
  • i_rx_rst_n: Resets the RX datapath, RX transceivers, and RX EMIB adapters.
    Note: When RX MAC is in reset, TX MAC is only able to transmit idles or remote fault indications if link fault signaling is enabled. You are unable to transmit the data. The o_tx_ready/o_tx_mac_ready remains low.
  • i_rst_n: Resets TX/RX datapaths, transceivers, and EMIB adapters.
    Note: The system PLL cannot be reset.
Table 32.  Reset Signals FunctionsIn this table, a tick (√) represents the block is reset by the specified reset signal.
Important: The F-Tile Ethernet Intel® FPGA Hard IP does not support clearing hard CSR registers back to the default values.
Reset Signal PHY Datapath Stats Soft CSRs
TX RX PCS TX PCS RX MAC TX MAC RX MAC TX MAC RX
Port Resets
i_rst_n  
i_tx_rst_n          
i_rx_rst_n          
i_reconfig_reset                
Register Resets
eio_sys_rst  
soft_tx_rst          
soft_rx_rst          
rst_tx_stats                
rst_rx_stats