F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
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7.13.1. Ethernet Reconfiguration Interfaces

You access Ethernet control and status registers of the F-Tile Ethernet Intel® FPGA Hard IP during normal operation using an Avalon® memory-mapped interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the i_reconfig_reset signal.
Note: The Avalon® memory-mapped interfaces are word-addressed. The address always aligns to 32-bit words. All register access described in this user guide is byte-based access. You need to convert each word address to a byte address by shifting right by two (dividing by 4). To access individual bytes, use the byte enable signals.
Table 56.  Ethernet Reconfiguration InterfaceThe signals in this interface are clocked by the i_reconfig_clk clock and reset by the i_reconfig_reset signal. This clock and reset are used for all the reconfiguration interfaces in the IP core.
Port Name Width Description

i_reconfig_eth_addr[13:0]

14 bits

Address bus for Ethernet control and status registers.

i_reconfig_eth_read

1 bit

Read request signal for Ethernet control and status registers.

i_reconfig_eth_write

1 bit

Write request signal for Ethernet control and status registers.

i_reconfig_eth_byteenable[3:0]

4 bits

Byte enable for Ethernet read and write request signals.

o_reconfig_eth_readdata[31:0]

32 bits

Read data from reads to Ethernet control and status registers.

o_reconfig_eth_readdata_valid

1 bit

Read data from Ethernet control and status registers is valid.

i_reconfig_eth_writedata[31:0]

32 bits

Write data for Ethernet control and status registers.

o_reconfig_eth_waitrequest

1 bit

Avalon® memory-mapped interface stalling signal for operations on Ethernet control and status registers.

Figure 54. Performing a Avalon® Memory-Mapped Interface Write on the Ethernet Reconfiguration Interface
The figure above shows how to write data using the Ethernet reconfiguration Avalon® memory-mapped interface.
  • When write begins while o_reconfig_eth_waitrequest is high, you must hold the write request (i_reconfig_eth_write) until o_reconfig_eth_waitrequest deasserts.

    A: When o_reconfig_eth_waitrequest deasserts, also deassert write on the next cycle.

  • When write begins while o_reconfig_eth_waitrequest is low:
    • B: The o_reconfig_eth_waitrequest signal asserts on the same clock cycle.
    • The write request holds until o_reconfig_eth_waitrequest deasserts.
    • C: On the next clock cycle after o_reconfig_eth_waitrequest deasserts, the write request (i_reconfig_eth_write)deasserts.
  • Write request can take a variable amount of time to complete.
  • You cannot perform read and write requests at the same time.
  • When multiple configuration bits are at the same address, a you need to perform a Read-Modify-Write operation to change the desired bits without changing the remaining configurations at the same location.
Figure 55. Performing a Avalon® Memory-Mapped Interface Read on the Ethernet Reconfiguration Interface
The figure above shows how to read data using the Ethernet reconfiguration Avalon® memory-mapped interface.
    • A: When read begins while o_reconfig_eth_waitrequest is high, you must hold the read request (i_reconfig_eth_read) until o_reconfig_eth_waitrequest deasserts.

      Then, the requested read data is available on the read port on the cycle when o_reconfig_eth_readdata_valid is high.

    • When read begins while o_reconfig_eth_waitrequest is low:
      • B: The o_reconfig_eth_waitrequest signal asserts on the same clock cycle as the read request (i_reconfig_eth_read).
      • C: The read request holds until o_reconfig_eth_waitrequest deasserts.

        Then, the requested read data is available on the read cycle when o_reconfig_eth_readdata_valid is high.

  • Read request can take a variable amount of time to complete.
  • You cannot perform read and write requests at the same time.
  • The Avalon® memory-mapped interface processes one read request at a time.