F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents
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9.1.1. Overview

The F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP (F-tile AN/LT IP) implements the auto-negotiation and link training for F-tile Ethernet ports. You must instantiate the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP and connect it to the Base Ethernet IP 20 Each F-tile AN/LT IP supports one Ethernet rate with same PMA type and FEC mode and can be shared with up to 16 Ethernet ports.

Figure 61.  F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP: Single Protocol and Multiple Ethernet Rates ExampleThe base Ethernet IP represents the F-Tile Ethernet Intel® FPGA Hard IP.

If you plan to integrate multiple Ethernet rates on your tile, you must instantiate multiple F-tile AN/LT IPs. For instance, to support 50G and 100G Ethernet rates with auto-negotiation and link training features, you must instantiate two F-tile AN/LT IP instances.

Figure 62.  F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP: Two Ethernet Rates ExampleThe base Ethernet IP represents the F-Tile Ethernet Intel® FPGA Hard IP.
20 Base Ethernet IP is equivalent to the F-Tile Ethernet Intel® FPGA Hard IP.