F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
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9.1.3. Functional Description

Figure 63. F-Tile Auto-Negotiation and Link Training Intel FPGA IP Block Diagram

Nios® CPU subsystem executes the AN/LT firmware. CSR blocks provide interface to the client logic.

Once configured and brought out of reset, the AN/LT functionality is automatic. To ensure the auto connection expected behavior, connect anlt_link port from F-Tile AN/LT IP to the Ethernet IP.

Based on configuration, the F-Tile AN/LT IP begins the auto-negotiation and link training flows and the Ethernet IP function is temporarily disabled. Once AN/LT is complete, the Ethernet IP re-enables into a data mode and behaves as a standard Ethernet port. If the RX Ethernet link goes down and the LX timer is enabled but the timer is expired, the AN/LT IP may restart the auto-negotiation flow. If the RX link goes down and the LF timer is disabled, the link remains in data mode.

You can access the F-Tile AN/LT IP CSR registers at any time to monitor status, change configuration, or interrupt or restart the flow for any of the Ethernet ports connected to that AN/LT IP instance.

AN/LT designs support both internal and external serial loopback for FGT PMAs. However, for FHT PMAs, only external serial loopback is supported natively with AN/LT designs. Internal serial loopback with FHT PMAs require a specific TX EQ setting to function properly. The NIOS set these settings once the internal serial loopback is enabled, When the internal serial loopback is disabled, the NIOS restores the original TX EQ settings, therefore negating the TX EQ settings specified during LT. To support internal serial loopback with AN/LT designs, you should first disable the AN/LT via CSR register settings. When the link is forced into data mode, you can enable the internal serial loopback. Alternatively, if the link already passed through AN/LT and is in data mode, you can enable the internal serial loopback.

Note: B0 FHT multi-lane designs support bonding by default in F-Tile AN/LT IP, and non-bonded FHT multi-lane designs are not supported.