F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents
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7.14.1. Time-of-Day Interface

The shared time-of-day (TOD) allows the IP core to reference all timestamps to the local time-of-day. The 96-bit timestamps are in IEEE 1588 v2 format.

Table 59.  Signals of the Time-of-Day (TOD) InterfaceThe time-of-day interface allows the IP core to reference all of its timestamps to the time of day as it is known locally.

All interface signals are clocked by the i_clk_tx_tod clock.

Signal Name

Width

Description

i_ptp_tx_tod[95:0] 96 Time-of-day (TOD), according to the local clock for the TX clock domain.
The timestamp is in IEEE 1588 v2 format.
  • [95:48]: represent seconds
  • [47:16]: represent nanoseconds
  • [15:0]: represent fractional nanoseconds
i_ptp_tx_tod_valid 1 Indicates the TX TOD signal is valid.
  • You assert the signal when i_ptp_tx_tod bus contains a valid time.
  • You deassert the signal for at least one clock cycle to indicate a significant change in the i_ptp_tx_tod value such as TOD reset or first TOD adjustment after system power up. The IP core deasserts o_tx_ptp_ready to indicate the TX egress timestamp is not valid.
i_ptp_rx_tod[95:0] 96 Time-of-day, according to the local clock for the RX clock domain.
The timestamp is in IEEE 1588 v2 format (96 bits).
  • [95:48]: represent seconds
  • [47:16]: represent nanoseconds
  • [15:0]: represent fractional nanoseconds
i_ptp_rx_tod_valid 1 Indicates the RX TOD signal is valid.
  • You assert the signal when i_ptp_rx_tod bus contains a valid time.
  • You deassert the signal for at least one clock cycle to indicate a significant change in the i_ptp_rx_tod value such as TOD reset or first TOD adjustment after system power up. The IP core deasserts o_rx_ptp_ready to indicate the RX egress timestamp is not valid.