F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents

7.14.5. PTP Status Interface

The PTP status interface lets applications using PTP functions know when the PTP timestamp logic is ready for use.
Table 63.  Signals of the PTP Status InterfaceAll interface signals are asynchronous.

Signal Name

Width

Description

o_tx_ptp_offset_data_valid 1 TX PTP offset data is valid.
When asserted, indicates that the PTP offset data for TX data path is available to read from the Avalon® memory-mapped interface registers:
  • ptp_tx_lane_calc_data_constdelay
  • ptp_tx_lane<n>_calc_data_offset
  • ptp_tx_lane<n>_calc_data_time
  • ptp_tx_lane<n>_calc_data_wiredelay,
where n is a range from 0 to number of active SERDES lanes.

The ptp_tx_lane0_calc_data_time signal is the captured time relative to the first TX SERDES lane.

o_rx_ptp_offset_data_valid 1 RX PTP offset data is valid.
When asserted, indicates that the PTP offset data for RX data path is available to read from the Avalon® memory-mapped interface registers:
  • ptp_rx_lane_calc_data_constdelay
  • ptp_rx_lane<n>_calc_data_offset
  • ptp_rx_lane<n>_calc_data_time
  • ptp_rx_lane<n>_calc_data_wiredelay,
where n is a range from 0 to number of active SERDES lanes.

The ptp_rx_lane0_calc_data_time signal is the captured time relative to the first RX SERDES lane.

o_tx_ptp_ready 1 TX PTP logic is ready for use.

When asserted, indicates that the PTP for TX data path is fully functional and the TX egress timestamp is valid within the supported accuracy range.

o_rx_ptp_ready 1 RX PTP logic is ready for use.

When asserted, indicates that the PTP for RX data path is fully functional and the RX ingress timestamp is valid within the supported accuracy range.