F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

2.6. IP Core Testbenches

Intel provides a testbench design example that you can generate for the F-Tile Ethernet Intel® FPGA Hard IP.

To generate the simulation testbench, follow these steps:
  1. In the F-Tile Ethernet Intel® FPGA Hard IP parameter editor, you must first set the parameter values for the IP core variation you intend to generate in your end product. If you do not set the parameter values for your design to match the parameter values in your end product, the testbench you generate does not exercise the IP core variation you intend
  2. Generate the example design.
  3. In the Intel® Quartus® Prime software, run logic generation to generate the tile-related files. The process generates full netlist for simulation and synthesis.

The testbench demonstrates a basic test of the IP core. It is not intended to be a substitute for a full verification environment.