F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/04/2023
Public
Document Table of Contents
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4.4.1. Features

F-Tile Ethernet Intel® FPGA Hard IP supports the following PTP features:
  • Latency registers to accommodate for delay of external PHY components
  • 10GE, 25GE, 50GE, 100GE, 200GE, and 400GE operating speed
  • 1-step update 1588v2 96-bit timestamp
  • 1-step update residence time in correction field
  • 1-step set UPD/IPv4 checksum to zero
  • 1-step update 2 byte of extended byte to ensure the UDP checksum remains correct
  • 1-step asymmetry delay adjustment in correction field
  • 1-step peer-to-peer mean path delay adjustment in correction field
  • PTP statistics to keep track of number of packets with a PTP timestamp operation in TX and RX path
  • Avalon® memory-mapped interface accessible configuration, debug, and status registers
  • Timestamp accuracy in Basic mode:
    • ± 3 ns for 10GE and 25GE modes
    • ± 8 ns for 50GE, 100GE, 200GE, and 400GE modes
  • Timestamp accuracy in Advanced mode:
    • ± 1.5 ns for 10GE, 25GE, 50GE, 100GE, 200GE and 400GE modes